Showing papers in "Journal of Vlsi Signal Processing Systems for Signal Image and Video Technology in 1990"
TL;DR: In each of these cases, it is shown that the asymptotic processor utilization is independent of the length of the pipeline; thus, linear speedup is achieved.
Abstract: We explore the practical limits on throughput imposed by timing in a long, self-timed, circulating pipeline (ring). We consider models with both fixed and random delays and derive exact results for pipelines where these delays are fixed or exponentially distributed random variables. We also give relationships that provide upper and lower bounds on throughput for any pipeline where the delays are independent random variables. In each of these cases, we show that the asymptotic processor utilization is independent of the length of the pipeline; thus, linear speedup is achieved. We present conditions under which this utilization approaches 100%.
63 citations
TL;DR: This paper has investigated the testing of systolic arrays built from a finite ring cell that has been proposed recently for digital signal processing functions, and shows that an array of such cells is remarkably easy to test for stuck-at faults.
Abstract: Testing large VLSI circuits is a difficult and challenging problem for designers. Large unstructured circuits are often impossible to test. The number of test vectors also tend to be large and difficult to generate using automated tools for testing. In this paper, we have investigated the testing of systolic arrays built from a finite ring cell that has been proposed recently for digital signal processing functions. The cell has been shown to allow encoding, decoding and general inner product type computations for residue number system applications, with considerable advantages over equivalent binary implementation. As a further feature, we show, in this paper, that an array of such cells is remarkably easy to test for stuck-at faults. Generating test vectors for these arrays is also straightforward.
14 citations
TL;DR: A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described and a technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation.
Abstract: A bit-level systolic array system for performing a binary tree Vector Quantization codebook search is described. This consists of a linear chain of regular VLSI building blocks and exhibits data rates suitable for a wide range of real-time applications. A technique is described which reduces the computation required at each node in the binary tree to that of a single inner product operation. This method applies to all the common distortion measures (including the Euclidean distance, the Weighted Euclidean distance and the Itakura-Saito distortion measure) and significantly reduces the hardware required to implement the tree search system.
7 citations
TL;DR: A single, efficient implementation of dynamic programming on alinear array using a new mapping methodology, which makes the design suitable for implementation on the well-known fault-tolerant Wafer Scale Integration model.
Abstract: In the paper we show a single, efficient implementation of dynamic programming on alinear array using a new mapping methodology. In this method, we start with a known 2-D array onto which the dynamic programming algorithm has been mapped. By partitioning and stretching, this 2-D array is mapped onto a linear array. We derive a data movement scheme to simulate the data streams and the computations in the 2-D array. This scheme is implemented usingfast/slow data channels. Compared to known designs in the literature our design uses constant storage in each PE, constant number of I/O lines and continuous I/O sequence. Besides, the data and control flow in the array is unidirectional. This property makes the design suitable for implementation on the well-known fault-tolerant Wafer Scale Integration model.
5 citations
TL;DR: It is shown that a simple model of a linear systolic array with serial input/output and one-way data communication can be used to solve some scheduling and graph problems efficiently.
Abstract: We consider a simple model of a linear systolic array with serial input/output and one-way data communication. We show that such an array can be used to solve some scheduling and graph problems efficiently. The systolic algorithms are developed in two stages. First an algorithm on a restricted type of sequential machine is constructed. Then the sequential machine algorithm is transformed into a systolic algorithm. The transformation can be done automatically and efficiently.
2 citations