Patent
Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches
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TLDR
In this article, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line is presented, where a determination is made as to whether the cache lines are in an exclusive, modified, invalid, or shared state.Abstract:
In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.read more
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References
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Patent
Hierarchical cache memory system and method
Wilson Andrew W,Frank Steven J +1 more
TL;DR: In this paper, the authors propose a cache coherency management scheme for a shared bus multiprocessor which includes several processors each having its own private cache memory, each private cache is connected to a first bus to which a second, higher level cache memory is also connected.
Patent
Cache coherency protocol for multi processor computer system
Darrel D. Donaldson,Mark N. Howard,David A. Orbits,John M. Parchem,David M. Robinson,Douglas D. Williams +5 more
TL;DR: In this paper, the authors propose a cache coherency protocol for multi-processor systems which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory.
Patent
Coupled memory multiprocessor computer system including cache coherency management protocols
TL;DR: In this article, a coherent coupled memory multiprocessor computer system with a plurality of processor modules (11a, 11b... ), a global interconnect (13), an optional global memory (15), and an input/output subsystem (17, 19) is disclosed.
Patent
Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed
TL;DR: In this article, the cache controller includes a set of latches coupled to the host bus which it uses to latch the state of host bus during a snoop cycle if the cache is unable to immediately snoop that cycle.
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