Proceedings ArticleDOI
AS/400 PowerPC compatible semi-custom technology
M. Gruver,N. Phan,T. Aipperspach,S. Hilker,J. Bartley +4 more
- pp 197-202
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This paper describes the technology and semi-custom design aspects of the AS/400 PowerPC chip set, which was designed and packaged in a multi-chip, high performance package to form the processor engine.Abstract:
This paper describes the technology and semi-custom design aspects of the AS/400 PowerPC chip set. In order to meet the growing demand for AS/400 system performance, a 6 ns cycle time was specified. This requirement, coupled with the desire for a short development cycle, drove the chip team to choose a semi-custom design style utilizing a mature BICMOS technology. Three semi-custom chips and one ASIC were designed and packaged in a multi-chip, high performance package to form the processor engine. >read more
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Proceedings ArticleDOI
A user's view of MCM-D/C packaging: is it worth the trouble?
TL;DR: In this paper, the authors describe why they chose Multi-Chip Modules with Thin-film wiring (MCM-D on C) for their latest AS/400 processor package, which consists of 5 layers of thin-film metal applied to the surface of a 30 layer ceramic substrate.
Proceedings ArticleDOI
AS/400 64-bit powerPC-compatible processor implementation
TL;DR: An implementation of the 64-bit PowerPC Architecture optimized for the IBM AS/400 commercial environment is described, and a 4-way rightly-coupled symmetric multi-processor system is one of several configurations supported by this implementation.
Proceedings Article
AS/400TM 64-bit PowerPCTM-Compatible Processor Implementaiton
TL;DR: A 4-way tightly-coupled symmetric multi-processor system is one of several configurations supported by this implementation of the 64-bit PowerPC Architecturen' optimized for the IBM AS,,400 Commercial environment.
References
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Proceedings ArticleDOI
VLSI design automation for the application system/400
TL;DR: The VLSI design automation process for the IBM AS/400 is highly focused on the dual goals of short design time and exhaustive verification, as well as high level language and synthesis and chip physical design, and system testing.
Proceedings ArticleDOI
IBM AS/400 processor technology
TL;DR: The architecture of the IBM AS/400 processor has unique silicon performance and density requirements which are addressed with 12.7 mm CMOS ASIC chips utilizing 0.8 mu m lithography and 0.5 mu m channel lengths.
Proceedings ArticleDOI
IBM AS/400 processor architecture and design methodology
Q.G. Schmierer,A.H. Wottreng +1 more
TL;DR: The architecture and design methodology used in the IBM AS/400 processor are briefly described and the designer's experiences with these new methods are highlighted.