Patent
Cascading PLL units for achieving rapid synchronization between digital communications systems
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TLDR
In this article, a clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between is presented, where the first device generates a first clock signal Fa and the second device produces a second clock signal Fb 2.Abstract:
A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb 2 . The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb 2 . The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb 2 . enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb 2.read more
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References
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Patent
Rate recovery device
TL;DR: In this article, a rate recovery device consisting of two servocontrol loops, one being a fast-acquisition loop and the other being a holding loop, is described.
Patent
Circuit arrangement for adjusting a system frequency
TL;DR: In this article, a PLL with a phase detector (PD2), a voltage controlled oscillator (VCO2), and a frequency divider (K) is presented. But the phase detector is not connected to the phase detectors.