Patent
Circuit for glitch-free switching of asynchronous clock sources
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TLDR
In this paper, the state machine provides output signals which are processed by a delay circuit to ensure that switches between clock sources only occur during an inactive period of the clock signals to prevent signal glitches.Abstract:
A circuit, including a state machine, e. g. a logic array and a set of controlled storage devices, receives conditioning signals, such as reset, power failure signals and signals fed back from the storage devices, and uses the signals to determine which of a number of clock sources is to be used in a system. The state machine provides output signals which are processed by a delay circuit to ensure that switches between clock sources only occur during an inactive period of the clock signals to prevent signal glitches. The circuit's output signal controls a number of AND gates, each of which gates a particular clock signal to an output line. When a power fail condition occurs, a switch between a first clock signal and a substantially lower frequency clock signal is required to conserve power. This is achieved by first switching to a synchronized lower frequency clock signal, and then to a non-synchronized lower frequency clock signal when the first clock signal is switched off since the synchronized low frequency clock signal is lost at this time when the clock source from which the first signal is generated is switched off to conserve power. A reverse process switches back to the high frequency clock without glitches when power returns.read more
Citations
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References
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Patent
Clock switching circuit and method for preventing glitch during switching
TL;DR: In this paper, a clock switching circuit comprises a multiplexer, a gate, a first detector, a second detector and a state machine, which is coupled to the output of the gate.
Patent
Multiple input clock selector
TL;DR: In this article, a multiple input clock selector is provided for switching asynchronously from one to another of a plurality of oscillators that generate clock signals having different frequencies, and the clock selector switches between oscillators as determined by select signals without producing runt pulses, metastable conditions, or other anomalous signals.
Patent
Glitch free clock select
TL;DR: In this article, a clock select circuitry is provided which allows CPU operation at one-half the crystal frequency or one half the crystal clock frequency under CPU control and circuitry is added to insure that the a glitch free clock change can be performed on the fly.
Patent
Clock signal switching circuit
TL;DR: In this article, a clock signal switching circuit with input terminals to receive a first clock signal and a second clock signal of a first frequency, and an output terminal to output one of the first and second clock signals by the frequency switching signal is defined.
Patent
Automatic synchronous switch for a plurality of asynchronous oscillators
TL;DR: In this paper, a switching circuit for automatically selecting one of a plurality of normally operable asynchronous oscillators is provided with a selection switch for selecting a new oscillator while the formerly selected oscillator is still producing an output.