Clock reproducing circuit

TLDR: In this paper, the authors proposed to realize both characteristics of high-speed clock synchronization and phase jitter suppression to eliminate effectively troubles of the time division multiple access system and so on, by switcing two different reproducing clocks of a clock reproducing circuit.

Abstract: PURPOSE:To realize both characteristics of high-speed clock synchronization and phase jitter suppression to eliminate effectively troubles of the time division multiple access system and so on, by switcing two different reproducing clocks of a clock reproducing circuit. CONSTITUTION:Input signal Si including clock components is branched into two by branching circuit 21, and one signal Si1 is applied to wide band filter 22 to extract clock components D, and amplitude fluctuation components of components D are eliminated by amplitude limiter 24, and the output of lmiter 24 is applied to switch 27. The other signal Si2 separated by circuit 21 is applied to narrow band filter 23 to extract clock components E, and amplitude fluctuation components of components E are eliminated by amplitude limiter 25, and the output of limiter 25 is applied to switch 27. Components D obtained by branching input signal Si into two are detected by detector 26, and the detected control signal is applied to swotch 27 where outputs of limiters 24 and 25 are input, and output signal So of switch 27 is switched from reproducing clock So1 or So2 to reproducing clock So2 or So1 by the control signal.