Patent
Closed-grid bus architecture for wafer interconnect structure
Charles A. Miller,John M. Long +1 more
TLDR
In this article, a closed-grid bus is used to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channels can concurrently communicate with all of the I/O pads.Abstract:
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.read more
Citations
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Patent
High performance probe system
TL;DR: In this article, a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads are used to provide signal paths between an integrated circuit (IC) tester and input/output, power and ground pads.
Patent
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TL;DR: In this paper, a probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a Wafer, while limiting undesirable effects of fan out on test results.
Patent
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TL;DR: A low-current pogo probe card for measuring currents down to the femtoamp region includes a laminate board having a layer of conductive traces interposed between two dielectric layers as discussed by the authors.
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TL;DR: In this paper, a direct current and a modulation signal are simultaneously applied to contact pads on a device under test, such as a laser diode, with a probe that reduces signal distortion and power dissipation by transmitting a modulated signal through an impedance matching resistor.
References
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Patent
Wafer-level burn-in and test
TL;DR: In this article, the authors describe a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-undertest (WUT), all disposed in a vacuum vessel so that the ASIC can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs.
Patent
System and method for evaluating agents in call center
TL;DR: In this paper, a call is received within a call center and has a plurality of agents, an automatic call distributor (ACD) server for routing calls to individual agents based on the proficiency skills of the agents, a interactive voice response (IVR) server, and in one aspect, a structured query language (SQL) server having a historical database.
Patent
Semiconductor wafer test and burn-in
James M. Leas,Robert William Koss,Horn Jody Van,George Frederick Walker,Charles Hampton Perry,David L. Gardell,Steve Leo Dingle,Ronald J. Prilik +7 more
TL;DR: In this article, an apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer is presented. But the apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on an integrated circuit wafer.
Patent
Apparatus for testing integrated circuits
TL;DR: A membrane probe (10, 12, 14, 16, 58, 144) for testing integrated circuits (56,138) while still on the wafer upon which they are manufactured includes a flexible visually clear and self planarizing membrane (26) having circuit traces (20) and ground shielding planes (14), terminating resistor (152) and active buffer chips (172) formed thereon Probe contact pads (36,38) electroplated on areas of the traces, and connector pads (32) plated on the membrane facilitate rapid detachable connection to a test fixture
Patent
Burn-in technologies for unpackaged integrated circuits
TL;DR: In this article, the authors present a method for burn-in of bare chips prior to assembly into a multichip module. Each die to be tested is positioned with its I/O pads positioned to face an interconnection test substrate which may be a silicon circuit board.