Patent
Cmos odd multiple repetition rate divider circuit
TLDR
The disclosed divider circuit as mentioned in this paper divides the repetition rate of an input signal by an odd integer to provide an output signal, which can be used to generate a small amount of chip area.Abstract:
The disclosed divider circuit divides the repetition rate of an input signal by an odd integer to provide an output signal. The divider includes at least four binary cells and either a NOR and a NAND gate. Each binary cell includes first and second inversely clocked transmission gates and first and second inverters. Selected output terminals of three of the binary cells are connected to the input terminals of the gate and the output terminal of the gate is connected to the input terminal of the fourth binary cell. The resulting circuit configuration lends itself to fabrication by CMOS processes and takes up only a small amount of chip area.read more
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Patent
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Patent
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References
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Patent
Electronically controlled timepiece using low power mos transistor circuitry
TL;DR: In this article, an ELECTRONIC OSCILLATOR OPERATING at a constant state of emergency was used as a wistle-watch for a series of transistor stages.
Patent
Pulse frequency dividing circuit
Okumura T,Tomisawa N,Uchiyama Y +2 more
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Patent
Control logic for linear sequence generators and ring counters
TL;DR: In this paper, a control logic for linear sequence generators and ring counters was proposed to prevent latch-up in the state having a linear sequence generator including a shift register with modulo-2 exclusive-OR feedback from the shift register to the input and feedback through binary counters.