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Patent

Communication device including multiple LO receivers

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TLDR
In this paper, a phase error compensation block is used to compensate for the effects of using the other-than-two divisor in a multi-band multi-channel receiver.
Abstract
Some embodiments of the present disclosure relate to multiband receivers that include at least one divider unit having a divisor that is other-than-two For example, in some embodiments the divisor is an odd integer (eg, three) Such divisors allow oscillators for respective receiver subunits in a multi-band receiver to have frequencies that are sufficiently different from one another so as to limit cross-talk interference there between, even when the receiver subunits are concurrently receiving data on adjacent channels To facilitate this other-than-two divisor, a phase error compensation block is often used to compensate for the effects of using the other-than-two divisor

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Citations
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TL;DR: In this paper, a detection module for detecting the presence of a spur and a determination of its frequency, a complex notch filter chain, and a frequency locked loop which ensures that the input spur is notch filtered even if it drifts after detection.
References
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Patent

Compensation of I-Q imbalance in digital transceivers

TL;DR: In this article, the authors propose a method for remotely compensating for I-Q imbalance wherein a data packet having a known signal is transmitted to a receiver for conversion by a quadrature demodulator.
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TL;DR: In this article, the authors proposed a method to compensate for quadrature impairments of an analog quadratures modulator and/or demodulator over a relatively wide signal bandwidth.
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TL;DR: In this article, a method and system for filter calibration using fractional-N frequency synthesized signals is presented, where a single-chip multi-band RF receiver enables generation of a LO signal by a PLL circuit within the single chip, and enables calibration of a frequency response for a filter circuit integrated within the chip.
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TL;DR: In this paper, a variable delay element inserts a variable time delay in an ADC clock signal that is applied to either the I-channel or the Q-channel ADC, which is used for mismatch between channels in an I/Q demodulator.