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Patent

Computer system and method for leasing memory location to allow predictable access to memory location

TLDR
In this article, a synchronization technique for shared-memory multiprocessor systems involves acquiring exclusive ownership of a requested memory location for a predetermined, limited duration of time, and if an "owning" process is unpredictably delayed, the ownership of the requested memory locations expires after a predetermined duration, thereby making the memory location accessible to other processes.
Abstract
A synchronization technique for shared-memory multiprocessor systems involves acquiring exclusive ownership of a requested memory location for a predetermined, limited duration of time. If an “owning” process is unpredictably delayed, the ownership of the requested memory location expires after the predetermined duration of time, thereby making the memory location accessible to other processes and requiring the previous “owning” process to retry its operations on the memory location. If the “owning” process completes its operations on the memory location during the predetermination duration of time, the ownership of the memory location by the “owning” process is terminated and the memory location becomes accessible to other processes.

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Citations
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Vehicle Control Device

TL;DR: In this paper, a required condition concerning a relationship among a road surface reaction force that may act from a side slip angle and a friction characteristic of the k-th wheel was established.
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Leases for blocks of memory in a multi-level memory

TL;DR: In this article, the authors describe a computing device that has two or more levels of memory, each level of memory having different performance characteristics, and the computing device receives a request to lease an available block of memory in a specified level for storing an object.
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Access control in a flash storage system

TL;DR: In this paper, the authors proposed a lease-based fencing system for a single primary storage controller with a time-limited lease window, where writes to a shared storage medium are permitted, while writes are denied for expired leases.
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Distributed management of a storage system

TL;DR: In this paper, the authors proposed a lease-based fencing system for a single primary storage controller with a time-limited lease window, where writes to a shared storage medium are permitted, while writes are denied for expired leases.
References
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Journal ArticleDOI

Linearizability: a correctness condition for concurrent objects

TL;DR: This paper defines linearizability, compares it to other correctness conditions, presents and demonstrates a method for proving the correctness of implementations, and shows how to reason about concurrent objects, given they are linearizable.
Journal ArticleDOI

Wait-free synchronization

TL;DR: A hierarchy of objects is derived such that no object at one level has a wait-free implementation in terms of objects at lower levels, and it is shown that atomic read/write registers, which have been the focus of much recent attention, are at the bottom of the hierarchy.
Journal ArticleDOI

Algorithms for scalable synchronization on shared-memory multiprocessors

TL;DR: The principal conclusion is that contention due to synchronization need not be a problemin large-scale shared-memory multiprocessors, and the existence of scalable algorithms greatly weakens the case for costly special-purpose hardware support for synchronization, and provides protection against so-called “dance hall” architectures.
Proceedings ArticleDOI

Simple, fast, and practical non-blocking and blocking concurrent queue algorithms

TL;DR: Experiments on a 12-node SGI Challenge multiprocessor indicate that the new non-blocking queue consistently outperforms the best known alternatives; it is the clear algorithm of choice for machines that provide a universal atomic primitive (e.g., compare_and_swap or load_linked/store_conditional).
Journal ArticleDOI

The performance of spin lock alternatives for shared-money multiprocessors

TL;DR: The author examines the questions of whether there are efficient algorithms for software spin-waiting given hardware support for atomic instructions, or whether more complex kinds of hardware support are needed for performance.