Patent
D flip-flop
Chi-Wah Kok,Yee Ching Tam +1 more
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TLDR
In this paper, a D flip-flop with a half-static slave stage or a master stage with clock gating by the input and output is described. But the clock gated circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the inputs and outputs are at the same logical state.Abstract:
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.read more
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References
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Patent
Multi-threshold mos circuits
TL;DR: A multi-threshold flip-flop (100a) includes a master latch (110), a slave latch (120), and at least one control switch as discussed by the authors, which can operate at high speed, has low leakage current, and can save the logic state when disabled.
Patent
Reducing power and area consumption of gated clock enabled flip flops
TL;DR: In this paper, a master latch implemented to receive feedback from a slave latch on a different input terminal than a input terminal on which data bits are received is used to minimize the number of transistors/area and/or power consumption requirements in implementing a flip-flop.
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Complementary pass transistor based flip-flop
Kitae Park,Hyo-sik Won +1 more
TL;DR: In this article, a complementary pass transistor based flip-flop (CP flipflop) with a relatively small layout area and operable at a high speed with reduced power consumption is provided.
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Method and system for reducing hazards in a flip-flop
TL;DR: In this paper, a method for reducing hazards in a flip-flop, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided.