Patent
Device for computing a sliding and nonrecursive discrete Fourier transform and its application to a radar system
Reads0
Chats0
TLDR
In this article, a non-recursive and sliding discrete Fourier transform for processing a pulse compression radar signal has been proposed, where each stage comprises two complex rotation operators, two adder-subtracters and two delay circuits and delivers a signal X k m+1 obtained from the following equations.Abstract:
A device for computing a nonrecursive and sliding discrete Fourier transform as applicable in particular to processing of a pulse compression radar signal has N identical and parallel stages (E k ) for receiving in each case samples of the input signal (e m+N ). Each stage comprises two complex rotation operators, two adder-subtracters and two delay circuits and delivers a signal X k m+1 obtained from the following equations: ##EQU1##read more
Citations
More filters
Patent
Slant transform/signal space crash discriminator
Tony Gioutsos,Jace L Allen +1 more
TL;DR: In this paper, a system and method for triggering a vehicle safety device in response to a crash or sudden vehicle deceleration includes conversion of an analog signal generated by an acceleration sensor and representative of instantaneous vehicle acceleration to a digital value and using a ROM lookup table to determine its natural log.
Patent
Wideband radar detector
Steven K. Orr,John Kuhn +1 more
TL;DR: In this article, a wideband radar detection apparatus includes a signal detection section, high rate signal processing section and a low rate processing section, which sweeps through a range of preselected frequencies and generates an output signal having a pair of single cycle sinusoids for every detected signal.
Patent
Long range police radar warning receiver
TL;DR: In this paper, a police radar warning receiver is disclosed including a DSP circuit having a correlator and a peak detector to provide after each sweep of a swept local oscillator a dynamic threshold for that sweep as affected by all prior sweeps and against which information from that sweep is evaluated to determine whether to generate an alarm or not.
Patent
Two dimensional fast Fourier transform converter
TL;DR: In this paper, a two-dimensional fast Fourier transform converter with a frame serial processing path is presented. But the parallel processors are organized for performing the row and column transformations in a highly parallel and efficient manner.
Patent
Long range police radar warning receiver with multiple array averaging
TL;DR: A police radar warning receiver includes a DSP circuit having a correlator, multiple array averager and a peak detector to provide after each sweep of a swept local oscillator respective dynamic thresholds associated with each averager array and against which information from that sweep is evaluated to determine whether to generate an alarm.
References
More filters
Patent
Efficient low-sidelobe pulse compression
TL;DR: In this article, the authors proposed a pulse compression system for use with step approximation to linear FM and rank coded signals to eliminate sampling errors and range time grating lobes while providing large pulse compression ratios comprising: a receiving circuit for receiving echo signals, a converting circuit for converting echo signals from the receiver to I and Q baseband signals without clock sampling, a sliding window discrete Fourier transform or fast Fourier Transform (FFT) circuit including a taped delay line and a plurality of resistor-type phase weighting networks and adders.
Patent
Method and apparatus for computing the discrete Fourier transform recursively
TL;DR: In this article, two parallel shift registers store and shift the real and imaginary components of the complex number X k + iY k, successively shifted one bit per strobe in response to receipt of new data.
Patent
Method and apparatus for sequencing addresses of a fast fourier transform array
TL;DR: In this paper, an apparatus and method for generating a specific sequence of addresses of values of an array stored in a digital memory is presented, where the addresses are generated by a first counter which generates a seed value and a second counter which produces a control value, the control value controlling a bit inserter and a programmable shifter.
Patent
Cordic FFT processor
TL;DR: In this article, an apparatus for performing a Fourier transform using Cordic techniques is presented, where digital words are pipelined through serial add/subtract stages to provide vector rotations without trignometric lookup tables or multiply operations.
Patent
Serial FFT processing unit
TL;DR: An FFT processing unit of simplified construction comprises one or more arithmetic stages serially connected, each stage has a plurality of recursive arithmetic paths each consisting of a delay element, a simplified multiplier for multiplying by ±1 and ±j where j = √-1, and an adder as mentioned in this paper.