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Patent

Division circuit for finite field

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TLDR
In this article, the inverse element of a divisor is calculated by multiplying the divident and the inverse elements of the divisors while converting one of them to a matrix expression, and then the quotient x/y is calculated in the vector expression.
Abstract
PURPOSE:To make a circuit scale compact and to accelerate calculation speed by calculating the inverse element of a divisor out of a divident and the divisor expressed by a vector with (m) bits on a finite field GF (2 ) by vector expression and multiplying the divident and the inverse element of the divisor while converting one of them to a matrix expression. CONSTITUTION:When a quotient x/y of two elements (x) and (y) on the finite field GF (2 ) is calculated, at first, an inverse element y of the first element (y) is generated with the vector expression by an inverse element generating circuit 3 and afterwards, multiplier circuits 1 and 2 convert the second element (x) to the matrix expression and multiply this element (x) in the matrix expression and the inverse element y in the vector expression. Then, the quotient x/y is calculated in the vector expression. In comparison with a conventional circuit using a ROM as three conversion tables, the circuit scale of the inverse element generating circuit 3 becomes about 1/3 and the inverse element generating circuit 3 is used only once. Thus, the circuit scale of the multiplier circuit on the finite field GF (2 ) is made compact and the calculation speed can be accelerated.

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