Patent
Dynamic random access memory (dram) refresh
TLDR
In this paper, a method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and a second refresh on a second portion of DRAM with a higher refresh rate.Abstract:
A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.read more
Citations
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Patent
Semiconductor memory device.
TL;DR: In this paper, the read circuit senses a change in a voltage of the bitline of a bitline, and applies a voltage which is different from the first voltage to the gate of the first transistor when it senses a voltage change.
Patent
Row hammer refresh command
Kuljit S. Bains,John B. Halbert,Christopher P. Mozak,Theodore Z. Schoenborn,Zvika Greenfield +4 more
TL;DR: In this paper, the memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer events, and sends one or more commands to the memory device to cause the device to perform a targeted refresh that will refresh the victim row.
Patent
Row hammer monitoring based on stored row hammer threshold value
Kuljit S. Bains,John B. Halbert +1 more
TL;DR: In this article, the detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row.
Patent
Row hammer condition monitoring
Zvika Greenfield,Kuljit S. Bains,Theodore Z. Schoenborn,Christopher P. Mozak,John B. Halbert +4 more
TL;DR: In this article, a system monitors data accesses to specific rows of memory to determine if a row hammer condition exists and indicates address information for the row whose access count reaches a threshold.
Patent
Method, apparatus and system for responding to a row hammer event
John B. Halbert,Kuljit S. Bains +1 more
TL;DR: In this article, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory devices.
References
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Patent
Semiconductor memory device and refresh period controlling method
Ito Yutaka,Hashimoto Takeshi +1 more
TL;DR: In this paper, the authors present a memory device including an error rate measurement circuit and a control circuit, carrying a BIST circuit, which reads out and writes data for an area for monitor bits every refresh period to detect an error count with the refresh period.
Patent
Variable refresh control for a memory
TL;DR: In this article, a variable refresh control circuit is used to adjust the refresh rate of a memory array using a capacitor for data storage, and a monitor circuit is provided for monitoring the stored logic state of each of the test memory cells.
Patent
Memory system and method using ECC to achieve low power refresh
Dean A. Klein,John F. Schreck +1 more
TL;DR: In this paper, the data from the rows of memory cells are read, and the stored syndromes are used to determine if there are errors in the read data and correct any errors that are found.
Patent
Method and system for minimizing power demands on portable computers and the like by refreshing selected dram cells
TL;DR: In this article, a RAM row refresh signal is generated to only a selected number of rows of memory cells within the random access memory stage, after a central processing unit has read a given software program to determine its data storage requirements.
Patent
Memory controller method and system compensating for memory cell data losses
TL;DR: In this article, the memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh, and the comparator compares the row addresses to row addresses from a refresh shadow counter that identifies the rows in the DRAMs being refreshed.