Error correction in sampled-data circuits

TLDR: In this paper, an inverse linear circuit for detecting decision errors according to whether its outputs satisfy the constraints, with means to combat propagation of the error in the inverse circuit, and reliability information in the form of magnitude and sign of apparent errors.

Abstract: Error correction in modems and similar sampled-data circuits that have outputs representable as outputs of a linear circuit with integer-valued impulse response when the integer-valued input sequence is subject to predetermined constraints. Integervalued tentative decisions and reliability information are formed and stored. A correction is made upon detection, on the basis of the constraints, of an error in the tentative decisions. Shown also are: an inverse linear circuit for detecting decision errors according to whether its outputs satisfy the constraints, with means to combat propagation of the error in the inverse circuit; reliability information in the form of magnitude and sign of apparent errors, especially storing only the extreme values of apparent errors in the sequence under review; constraints in form of predetermined finite range of integers and detection with an inverse circuit on basis of values falling outside of the finite range, also combating propagation by replacement of erroneous value with closest substitute satisfying the constraints; and impulse responses of the form 1 + OR - Dn, where n integer, and division of tentative decisions and memory into related groups.