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Patent

ESD detection circuit and related method thereof

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TLDR
In this paper, an electrostatic discharge (ESD) detection circuit is provided, which includes a first power pad for receiving a first supply voltage, a second power pad and a second supply voltage.
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Apparatus and methods for transient overstress protection with active feedback

TL;DR: In this article, an approach for providing transient overstress protection with active feedback is described, which includes a transient detection circuit, a bias circuit, clamp circuit, and sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping.
Patent

Apparatus and methods for actively-controlled trigger and latch release thyristor

TL;DR: In this article, an active trigger and latch release circuit was proposed to detect transient overstress events at the signal node based on the voltage of the dummy supply node. But the active trigger was not used to control the SCR's activation voltage.
Patent

High voltage clamps with transient activation and activation release control

TL;DR: In this article, high voltage clamps with active activation and activation-release control are provided to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events.
Patent

Apparatus and methods for actively-controlled transient overstress protection with false condition shutdown

TL;DR: In this article, a high-voltage tolerant actively-controlled transient overstress protection with false condition shutdown is presented, in which a clamp circuit is electrically connected between a first node and a second node, and a bias circuit biases the clamp circuit.
References
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Patent

Circuit for electrostatic discharge protection

TL;DR: In this article, the gate-to-body capacitance in the current shunting device (135) was used to reduce the delay of the trigger circuit in the RC delay circuit.
Patent

Dual-node capacitor coupled MOSFET for improving ESD performance

TL;DR: In this paper, a dual-node capacitor coupling technique is used to lower the trigger voltage and to improve the uniform turn-on of a multi-finger MOSFET transistor.
Patent

ESD detection circuit

TL;DR: An ESD detection circuit which includes a triggering circuit for generating an ESD trigger signal when the detection circuit is in ESD mode, a bias circuit for providing at least a first bias voltage and a second bias voltage for controlling the operation of the triggering circuit, and an activating control circuit for activating the trigger controlling circuit and triggering circuit to enter the ESD phase according to a voltage level at a first node.