Patent
Fault-tolerant real time clock
TLDR
In this paper, three hardware real-time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails, but a power supply or processor failure will not cause a clock supplying other processors to fail.Abstract:
Three hardware real time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails. A power supply or processor failure will not cause a clock supplying other processors to fail. Output of voted master clock pulses to the counter in every subcircuit is inhibited until all power supplies are turned on and stabilized, and the time base of the real time clock pulses is variable. The output pulses of all subcircuits are voted on and the voter output is the real time clock. The master clock can be the processor clock.read more
Citations
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Patent
Fault-tolerant computer system with online recovery and reintegration of redundant components
Douglas E. Jewett,Tom Bereiter,Bryan Vetter,Randall G. Banton,Richard W. Cutts,Donald C. Westbrook,Krayn W. Fey,John Posdro,Kenneth C. Debacker,Nikhil A. Mehta +9 more
TL;DR: In this article, a fault-tolerant configuration of multiple identical CPUs executing the same instruction stream, with multiple identical memory modules in the address space of the CPUs storing duplicates of the same data, is presented.
Patent
Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
Takashi Hotta,Kozaburo Kurita,Masahiro Iwamura,Hideo Maejima,Shigeya Tanaka,Tadaaki Bandoh,Yasuhiro Nakatsuka,Kazuo Kato,Sin-ichi Sinoda +8 more
TL;DR: An information processing system having an original clock oscillator for delivering at least one original clock signal defined as a first clock signal and a plurality of information processing units supplied with the original clock signals is defined in this article.
Patent
Method and apparatus for synchronizing a plurality of processors
TL;DR: In this article, a synchronizing system for a plurality of processors is presented, where each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state.
Patent
Fault tolerant memory system
Robert L. Papenberg,Runchan D. Yang,David H. Wotring,Mohammad F. Rydhan,Paul Voloshin,Mohamed M. Talaat +5 more
TL;DR: In this article, a fault tolerant clock system is provided by utilizing redundant clocks which are maintained in synchronization, with voting circuit serving to select one of a plurality of matching clock signals for use.
Patent
Synchronized fault tolerant clocks for multiprocessor systems
TL;DR: In this article, a fault-tolerant synchronized operation of the Time of Day (TOD) clocks of the respective data processors in a multiprocessor complex is described.
References
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Journal ArticleDOI
Synchronization and Matching in Redundant Systems
TL;DR: A novel mutual feedback technique, called "synchronization voting," is introduced that does not have vulnerability to common-point failures and is described in the appendix—a fault-tolerant crystal-controlled clock.
Journal ArticleDOI
Microcomputer reliability improvement using triple-modular redundancy
TL;DR: This work examines the issues that affect the effectiveness of TMR for transient recovery and the reliability of semiconductor memory systems, and shows how careful application can improve the mission time of a small system by a factor of 3 or more.
Patent
Fault-tolerant clock system
TL;DR: In this article, a fault-tolerant clock system for providng digital timing signals (system clock signals) is provided by a plurality of clock sources, each clock source receives as inputs the generated clock signals from all the other clock sources and contains receiver circuitry to derive a system clock signal from said clock sources which is the consensus clock signals of the other sources.
Book
Microprocessors and programmed logic
TL;DR: This paper presents a meta-modelling framework for programmable logic devices that automates the very labor-intensive and therefore time-heavy and expensive process of designing and testing microprocessor systems.
Patent
System clock for electronic communication systems
TL;DR: In this article, the system clock is designed in such a way that a single failure of any kind will not prevent the generation of clock pulses, and the clock card is wired for redundant operation.