Flip-flop circuit

TLDR: In this paper, a logic circuit activating/inactivating to a cross coupling path on the way of the path of a master flipflop based on an output signal of a slave flip-flop and a clock signal was inserted.

Abstract: PURPOSE:To obtain the circuit with high reliability without causing malfunction by inserting a logic circuit activating/inactivating to a cross coupling path on the way of the path of a master flip-flop based on an output signal of a slave flip-flop and a clock signal CONSTITUTION:An AND gate 1 and a NOR gate 3 constitute the 1st composite inverse logic circuit 21 and an AND gate 2 and a NOR gate 4 constitute the 2nd composite inverse logic circuit 22 Their input/output terminals are coupled in crossing to constitute a master flip-flop 31 and AND gates 5, 6 and OR gates 51, 52 are inserted on the way of the coupling path An OR gate 7 and a NAND gate 9 constitute the 3rd composite inverse logic circuit 23 and an OR gate 8 and a NAND gate 10 constitute the 4th composite inverse logic circuit 24 Their input/output terminals are coupled in crossing to constitute a slave flip-flop 32 Thus, before positive feedback from the slave flip-flop 32 is established, the positive feedback is established forcibly by using a clock signal CK, then no malfunction is caused