Patent
Four mode microcomputer power save operation
Jeffrey R. Teza,Kenneth A. Lies +1 more
TLDR
In this paper, a calculator with constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups is presented, which enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or selectively connect in combination the first and second switched voltages.Abstract:
A calculator having constant memory utilizing a low power microcomputer with on-chip memory capability, and multiple partition power control of circuit groups Incorporation of a first and second switched negative voltage and a non-switched negative voltage enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal RAM, or to selectively connect in combination the first and second switched voltages In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved Power consumption less than conventional CMOS is obtainableread more
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Patent
Power management for a laptop computer with slow and sleep modes
TL;DR: In this article, a power manager within a portable laptop computer provides power and clocking control to various units within the computer in order to conserve battery power, including transistor switches controlled by the power manager.
Patent
Low-power, standby mode computer
James F. Cole,James H. McNamara +1 more
TL;DR: In this article, a method and apparatus for configuring a computer in low-power mode is provided, where dynamic random access memory is refreshed by a battery powered system in order to maintain the memory contents.
Patent
Apparatus for reducing computer system power consumption
TL;DR: In this paper, a battery-powered computer system monitors the address bus to determine when selected peripheral devices have not been accessed for a preset amount of time, and when the preset amount has passed the system powers itself down and stops the system clock, placing it in a standby mode.
Patent
Power conservation in microprocessor controlled devices
Richard A. Perry,Vernon L. Stant +1 more
TL;DR: In this paper, the authors propose a microprocessor controlled device with a low power, low performance, low speed processor and a high power, high performance, high speed processor for performing computationally intensive foreground tasks.
Patent
Computer power management system
Leroy D. Harper,Grayson C. Schlichting,Ian H. S. Cullimore,Douglas A. Hooks,Gavin A. Bradshaw,Biswa R. Banerjee,John P. Fairbanks,Roderick W. Stone +7 more
TL;DR: In this article, a low power management system including both hardware and software is provided for a battery powered portable computer, which includes the capability to turn off clock signals (not shown) to various sections of the computer based upon demand.
References
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Patent
Reducing power consumption in calculators
TL;DR: In this paper, the duty cycle of the power and clock supplied to the calculator is reduced to maintain (without displaying) selected stored information but to further reduce the rate of power consumption.
Patent
Combined timekeeper and calculator with low power consumption features
TL;DR: In this article, a combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signal, and a processor stage responsive to the supply of the clock signals for performing the operations required for the timekeeper mode and calculator mode.