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Hierarchial memory system with separate criteria for replacement and writeback without replacement

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TLDR
In this paper, the write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the writeback of written-to segments to the base memory without replacement is accomplished according to an age since first write algorithm.
Abstract
In a memory system having a cache memory and a bulk memory, write-back of data segments in the cache memory to the bulk memory for replacement purposes is accomplished in accordance with a least recently used algorithm while the write-back of written-to segments to the bulk memory without replacement is accomplished in accordance with an age since first write algorithm.

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Multiprocessor digital data processing system

TL;DR: In this paper, a multiprocessor digital data processing system comprises a plurality of processing cells (18A to 18R, 34A to 34F, 38A, 38B) arranged in a hierarchy of rings.
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References
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Patent

System for facilitating the copying back of data in disc and tape units of a memory hierarchial system

TL;DR: In this paper, a multi-level or hierarchial memory system for a multi processing system in which two or more processing units access the memory system has been proposed, with two types of memory units on each level with the exception of the lowest level.
Patent

Multi-processing system with a hierarchial memory having journaling and copyback

TL;DR: In this paper, a hierarchical memory system for multi-processing systems with two different types of memory units on each level is described, the data store and the copy back data store in each level are on two different power systems and transfers of the changes to the next lower level are done in the order in which the change entered in the copyback store with the oldest entry being the first to be copied back.
Patent

Instruction retry mechanism for a data processing system

TL;DR: In this paper, an instruction retry mechanism is proposed to enable a digital data processing system having main, buffer and local stores to restart and, in most cases, recover from an error or failure in the processor hardware associated with the buffer and the local stores.
Patent

Memory hierarchy system with journaling and copy back

TL;DR: In this article, a hierarchical memory system has two memory units on each level, a data store and a copy back store, which contains all the changes that have been made in that data either by addition or modification.
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Cache memory store in a processor of a data processing system

TL;DR: In this article, the cache store is operated in parallel to the request for data information from the main memory store and a successful retrieval from the cache cache store aborts the retrieval from a main memory.
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