Patent
Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof
TLDR
In this article, an integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle; conductive traces directly on the leads.Abstract:
An integrated circuit packaging system and method of manufacture thereof includes: leads and a paddle; a first encapsulant molded between the leads and the paddle, the first encapsulant thinner than the leads; a non-conductive layer over the paddle; and conductive traces directly on the leads, the first encapsulant, and the non-conductive layer.read more
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Patent
Silicon-on-plastic semiconductor device with interfacial adhesion layer
TL;DR: In this article, a semiconductor device with a polymer substrate and an interfacial adhesion layer over the polymer substrate is described, and methods for manufacturing the same are described. But the authors do not discuss the fabrication process.
Patent
Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
TL;DR: In this paper, a printed circuit module with a thinned die attached to the printed circuit substrate is described, where the die has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10 3 Ohm-cm.
Patent
Encapsulated dies with enhanced thermal performance
TL;DR: In this article, a plurality of flip-chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top of the carrier to encapsulate the plurality of flips.
Patent
Method for manufacturing an integrated circuit package
TL;DR: In this paper, a printed circuit board is provided with semiconductor die, which includes a back-end-of-line (BEOL) region, a Front-End-Of-Line (FEOL), and a semiconductor handle such that the BEOL region, the FEOL region and the handle are stacked.
Patent
Flip chip module with enhanced properties
Julio C. Costa,Thomas Scott Morris,Jonathan Hale Hammond,David Jandzinski,Stephen Parker,Jon Chadwick +5 more
TL;DR: In this paper, a flip chip module with at least one flip chip die is described, and a first mold compound is disposed on the top surface of the carrier, where a second mold compound resides over the substrate and provides a first recess over the first flip-chip die, where the first recess extends to a first die surface.
References
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Patent
Stacked semiconductor packages and method for the fabrication thereof
TL;DR: In this paper, a method for fabricating a stacked semiconductor package includes providing a substrate and mounting a first semiconductor device on the substrate, and an interposer is supported above the first device opposite the substrate.
Patent
Method for manufacturing fine pitch lead frame
TL;DR: In this paper, a fine pitch lead frame and a method for manufacturing the same is described, and examples of various methods for forming the lead frame in different configurations are also disclosed, including an additional etching, stamping out the leads with a finely tapered stamp tool punch or using conventional stamp tool punches in conjunction with finer stamp tool punching to create the fine pitch tip.
Patent
Stacked integrated circuit package system
TL;DR: A stacked integrated circuit package system as mentioned in this paper consists of a base integrated circuit having a base encapsulation with a cavity therein and a base interposer exposed by the cavity, and a top integrated circuit over the intermediate integrated circuit.
Patent
Pre-molded leadframe and method therefor
TL;DR: In this article, a pre-molded leadframe for use in a semiconductor package is presented, where a first molding material is formed in the leadframe to expose the upper surface of the die pad and the upper surfaces of the plurality of leads.
Patent
Integrated circuit packaging system with leads and method of manufacture thereof
TL;DR: An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the Lplated Lead; and an encapsulant encapsulating the LPL and the die as discussed by the authors.