Integrated latch circuit

TLDR: In this paper, the decoding circuit is used to reduce the number of latch circuits to X+Y circuits when the value of N is greater, by encoding, latching and decoding so that X + Y can be minimized at N = X.

Abstract: PURPOSE:To enable to remarkably reduce the number of latch circuits to X+Y circuits when the value of N is greater, by encoding, latching and decoding so that X+Y can be minimized at N=X.Y when the number of input and output terminals is N. CONSTITUTION:The decoding circuit 55 is provided to produce the output corresponding to 3X4=12 sets in response to the information of 7 sets of memory circuts 54. The signal corresponding to the output terminals T1-T12 of 12 sets, is converted into the signal having the weight of three types a-c and four types d-g at the encoding circuits I and II, each is stored to seven sets of memory circuits 54, and the output A-C and D-G are fed to the decoding circuit 55, the output is obtained as 12 types of signals AD, AE...CF, CG corresponding to the input and output, they are positively fed back to the input via the output circuit 51, and the output corresponding to the inputs can be obtained at 12 sets of terminals T1-T12. That is, the latch circuits required to obtain 12 sets of input and output terminals can be seven, and this means the number is smaller than conventional circuits by as many as five.