Patent
Level shift circuit and semiconductor integrated circuit
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TLDR
A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in reverse phase to generate an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel and two n-channel MOS transistors are connected in series between a first voltage terminal and a second voltage terminal.Abstract:
A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.read more
Citations
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References
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Patent
CMOS low power mixed voltage bidirectional I/O buffer
TL;DR: In this paper, the authors describe the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic-level signals to drive the final output stage which outputs a selectable logic level signal.
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Level converter including wave-shaping circuit and emulator microcomputer incorporating the level converter
TL;DR: The second β values of the first and second N-channel transistors are more than 50 times as large as the first β values as mentioned in this paper, which is more than 20 times larger than the first µ-β values of both N and P transistors.
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Circuit and method for an integrated level shifting latch
Kevin M. Ovens,Thomas C. Shinham +1 more
TL;DR: In this article, an integrated circuit (IC) comprising an integrated level shifting latch for I/O is presented, where the level shift and latch may operate differentially on the data signal.
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Digital signal level translator
TL;DR: A low static power, digital signal level translator for translating an unbalanced digital signal to a balanced digital signal with a greater dynamic signal range includes two complementary MOSFET latches and a complementary output buffer amplifier as discussed by the authors.
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Data output circuit for semiconductor device with level shifter and method for outputting data using the same
Soo-Hwan Kim,Young-Ho Suh +1 more
TL;DR: In this paper, a data output circuit for a semiconductor device with a level shifter and a method for outputting data using the same is presented, which includes an output buffer for receiving and latching an input data signal with a first voltage range in response to a clock control signal to provide a pair of output data signals.