Patent
Low power flip-flop circuit
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TLDR
In this paper, a low-power flipflop circuit is provided to reduce the power consumption by removing a switching operation between an output buffer and an internal clock generation circuit when an input signal of a flip flop is not changed.Abstract:
PURPOSE: A low-power flipflop circuit is provided to reduce the power consumption by removing a switching operation between an output buffer and an internal clock generation circuit when an input signal of a flipflop is not changed CONSTITUTION: A low-power flipflop circuit includes a latch, a comparison circuit(430) and an internal clock generation circuit(440) The latch is used for receiving and maintaining an input signal according to an internal clock signal The comparison circuit(430) is used for comparing the input signal to an output signal of the latch The internal clock generation circuit(440) is used for receiving an external clock signal and generating an internal clock signal The internal clock generation circuit is used for controlling a path of the external clock signal, generating the delayed and inverted external clock signal, and generating the internal clock signal The internal clock signal is generated by performing a NAND operation for the external clock signal and the delayed and inverted external clock signal The internal clock signal is synchronized with the external clock signalread more
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