Patent
Memory management for high speed media access control
TLDR
In this article, the need in the art for memory management for high speed media access control is addressed, and a flexible memory architecture is disclosed in which two configurations may be selected.Abstract:
Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.read more
Citations
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References
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Patent
Memory organization in a switching device
Pradeep Sindhu,Dennis C. Ferguson,Bjorn O. Liencres,Nalini Agarwal,Hann-Hwan Ju,Raymond Marcelino Manese Lim,Rasoul Mirzazadeh Oskouy,Sreeram Veeragandham +7 more
TL;DR: In this paper, a router (20) switches data packets from a source (10) to a destination (30) in a network in which the router includes two or more memory banks.
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Data exchange system comprising portable data processing units
TL;DR: In this article, the structure of the data elements and the data references as well as other references is chosen in such a way that a very efficient use of the restricted memory space of e.g. smart cards is obtained.
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TL;DR: In this article, the structure of the data elements and the data references, as well as other references, is chosen in such a way that a very efficient use of the restricted memory space of, for example, smart cards is obtained.
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TL;DR: In this paper, a traffic manager for a network switch input or output port stores incoming cells in a cell memory and later sends each cell out of its cell memory toward one of a set of forwarding resources such as, for example, another switch port or an output bus.
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Hierarchical prioritized round robin (hprr) scheduling
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