Patent
Memory request arbitrator
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TLDR
In this paper, a memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors.Abstract:
A memory request arbitrator is provided for selecting one of a plurality of requesting devices, such as microprocessors, which may make a request to access a memory device common to the plurality of requestors. Requests from the devices are applied in common as a portion of an address to a read only memory, a priority sequencer providing another portion of the address. The read only memory provides a selection signal to the selected requestor. The priority sequencer is periodically updated to thereby change the priority of requestors such that priority is given to each of the requestors over time. The priority sequencer may be temporarily disabled to thereby allow a requestor a "back-to-back" memory access for a multi-cycle memory instruction. Finally, the initial state of the request lines is checked upon system start up to determine whether any of the request lines are unused. Only those request lines associated with presently operating requestors are able to provide request signals to the read only memory.read more
Citations
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Patent
Distributed arbitration apparatus and method for shared bus
TL;DR: In this article, each user of an intercommunicastion bus is associated with a distinct channel of an arbitration bus and maintains a priority record indicating its current priority status against each other user.
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Conditional carry scheduler for round robin scheduling
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References
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Patent
System bus arbitration, circuitry and methodology
TL;DR: In this paper, a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit.
Patent
Arbitration scheme for a multiported shared functional device for use in multiprocessing systems
TL;DR: In this paper, an arbitration network for use in a data multiprocessing system that includes a functional unit such as a memory module, that is shared by several requestor devices, such as data processors, wherein access is granted to the shared functional unit through a common data bus on a rotating priority basis, is presented.
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Distributed bus arbitration method and apparatus
TL;DR: In this paper, a bus interconnects a plurality of elements to form a distributed signal processing system when two or more elements attempt to use the bus simultaneously, a method of arbitration occurs whereby each element places its element arbitration code on assigned lines of the bus forming a composite complementary code.
Patent
Multilevel priority arbiter
TL;DR: In this article, a multi-level arbiter for resolving multiple requests for access to a shared facility is proposed, which includes a plurality of loop arbiters, each including a polling circuit to test each of a pluralityof units for a request for accessing the shared facility.
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Distributed first-come first-served bus allocation apparatus
TL;DR: In this paper, first-come-first-served bus allocation is used to assign positions in the ordinal ranking concurrent with other activity on the data bus, such as requests from other devices for control of a data bus.