Patent
Method and apparatus of reducing transfer latency in an SOC interconnect
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TLDR
In this article, the authors proposed a method and apparatus for reducing transfer latency in a system on a chip, where the bus master, a bus slave and an arbiter are in electronic communication there between.Abstract:
Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.read more
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References
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Patent
Microprocessor architecture capable of supporting multiple heterogeneous processors
TL;DR: In this paper, the authors propose a memory control unit for controlling access by one or more devices within a processor to a memory array unit external to the processor via ports of the processor.
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Jay C. Pattin,James S. Blomgren +1 more
TL;DR: In this paper, DRAM row hits and misses are maximized by reordering DRAM requests from multiple processors to maximize DRAM rows hits and minimize row misses, and a row counter is reset for every new access but is incremented with a slow clock while the row is open but not being accessed.
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