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Method and circuit arrangement for establishing frame synchronisation in a time-division multiplex system

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TLDR
In this paper, an imitation frequency of less than one bit per frame was calculated for a predetermined frame alignment word (12 bits) for a time-division multiplex frame structure.
Abstract
For time-division multiplex frame structures previously used, an imitation frequency of less than one per frame can be calculated for a predetermined frame alignment word (12 bits). Assuming a frame structure which is built up with octets, an imitation frequency of greater than nine per frame is obtained for an 8-bit frame alignment word. It is the object of the invention to establish fast and reliable frame synchronisation for such frame structures having an imitation frequency of greater than one. For this purpose, all bit patterns which correspond to the frame alignment word are first determined in a search mode for the duration of one time frame, and an information item on their position in time is in each case stored. In a following comparison mode, it is determined for the duration of the next time frame, in each case at the times stored, whether a frame alignment word is again present. The respective yes/no result is evaluated for establishing frame synchronisation.

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Synchronizing method for sdh systems as well as method of and circuit arrangement for identifying different data structures

TL;DR: In this article, a method is disclosed for synchronizing a system frame-structured in accordance with a digital synchronous hierarchy, particularly as specified in CCITT G.708, where one frame sync word is detected, and then a first pointer (AU-4) is read which is spaced a predetermined distance from the sync word and addresses a cellstructured data area.
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Synchronising frame structure in sync. digital hierarchy

TL;DR: In this article, the path overhead reader (POH) is switched to a cell header decoder (CELL) which in turn is switched (S3) to the output line (AL).
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Packet synchronization detector

Gerd Spalink
TL;DR: In this paper, a packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet according to the present invention comprises a synchronization pattern detector and several synchronization state machines.
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Synchronisation monitoring installation for digital systems

TL;DR: In this article, the comparators (V1, V2, V3) monitor several frame synchronisation words and the multiplexer (MUX) is controlled so that the results of the monitoring process on the input of the switches can be supplied cyclically at the output of the MUX.
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Verfahren zur Rahmensynchronisation eines Empfangssignals

TL;DR: In this article, a method for frame-synchronising a receive signal with a signal structure which has successive signal frames, each with a test sequence and a data sequence, is presented.
References
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TDM transmission system with constant synchronisation derivation - compares bit patterns from data with bit pattern from frame

TL;DR: In this paper, the bit patterns formed from the received data are compared with the specific bit pattern of the frame synchronisation symbol, and a signal is used to trigger a flywheel circuit with the periodicity of the time frame when the signal appears within a given time interval.