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Patent

Method and device for monitoring Ethernet clock synchronization

Yin Erfei
TLDR
In this paper, the authors presented a method and device for monitoring Ethernet clock synchronization, where a slave clock device returns a delay request message to a master clock device, and the delay request messages carries link delay information between the master clock devices and the slave clock devices.
Abstract
The embodiment of the invention provides a method and device for monitoring Ethernet clock synchronization. In the method, a slave clock device returns a delay request message to a master clock device, and the delay request message carries link delay information between the master clock device and the slave clock device of a last time hack cycle, determined by the slave clock device, so that the master clock device is enabled to determine a time deviation between the master clock device and the slave clock device and according to whether the time deviation is smaller than a set time deviation threshold, whether to send alarm information is determined. Because in the method, the slave clock device returns the determined link delay information between the slave clock device and the master clock device to the master clock device from the master clock device so that the master clock device is enabled to determine a time hack condition of the slave clock device so as to achieve an objective of monitoring of the slave clock device and thus precision demands of time synchronization are ensured and loss caused by inaccuracy of time hack is reduced.

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Citations
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Patent

Clock synchronization method and system

Yin Erfei
TL;DR: In this paper, a clock synchronization method and system for software defined networks (SDN) is presented. But the clock synchronization is based on the synchronization of a master clock and a first switch corresponding to the master clock.
Patent

Time synchronization method and device

Li Hang
TL;DR: In this article, the authors proposed a time synchronization method and device that comprises the steps of determining and storing a difference value between a server security clock and a server system clock according to a set security clock when a target STS (Security Time System) server initially operates.
Patent

Synchronous time comparing equipment of redundant Ethernet, system and method thereof

Liu Wei
TL;DR: In this paper, a synchronous time comparing equipment of a redundant Ethernet, a system and a method thereof is presented, where the equipment comprises a redundancy exchange unit, at least three time stamp generation units, a message processing unit and a time base unit.
Patent

Distributed network clock synchronization system

TL;DR: In this paper, the authors proposed a distributed network clock synchronization system, in which a clock source and at least one level of slave equipment are progressively connected to the clock source to achieve clock synchronization.
Patent

Control method of regional clock system

TL;DR: In this paper, a control method of a regional clock system is described, where a workstation is provided with a main processing module, a standby processing module and a time input module.
References
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Patent

Mechanism For Making Delay From Network Elements Transparent To IEEE 1588 Protocols

TL;DR: In this paper, the authors present an approach for making legacy network elements transparent to IEEE 1588 Precision Time Protocol operation by using smart interface converters to provide transparent clock or boundary clock operation.
Patent

Validity judgment method of clock synchronous source device and device

Bin Wang
TL;DR: In this article, the validity judgment method of a clock synchronous source device and a device is characterized in that: an announce message and a sync message sent by a clock source device is received from a clock device, and a delay_req message is sent to the clock source devices; after the clock device receives the delay-req message, a delay-resp message is replied; and if the situation that the announce message, the sync message and the delay_resp message are time-out is detected by the clock devices, then the uplink and downlink two-way