Patent
Method and system for merging clocks from multiple precision time protocol (ptp) clock domains
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TLDR
In this paper, a method for synchronizing a slave clock in a Time Sensitive Network (TSN) that includes multiple Precision Time Protocol (PTP) clock domains is disclosed. But the method is limited to the case of a single PTP clock.Abstract:
Embodiments of a method and device are disclosed. In an embodiment, a method for synchronizing a slave clock in a Time Sensitive Network (TSN) that includes multiple Precision Time Protocol (PTP) clock domains is disclosed. The method involves determining parameters related to multiple PTP clock domains, assigning domain-specific weights to the multiple PTP clock domains based on the determined parameters, generating a control signal for a clock parameter using the domain-specific weights assigned to the multiple PTP clock domains, and adjusting the clock parameter of a slave clock in response to the control signal.read more
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Patent
Fault tolerant clock network
Eric John Spada,Yongbum Kim +1 more
TL;DR: In this paper, a fault tolerant and redundant grand master clock scheme was proposed to reduce or eliminate precision time transition caused by a network link or device failure, where the primary and backup clocks may be concurrently operated.
Proceedings ArticleDOI
A master redundancy technique in IEEE 1588 synchronization with a link congestion estimation
Takahide Murakami,Yukio Horiuchi +1 more
TL;DR: A novel best master clock (BMC) algorithm to take account of link congestion between master and slave nodes to improve the availability of synchronization in IEEE 1588 is proposed.