Patent
Multi-layer semiconductor device
TLDR
A multi-layer semiconductor device comprising of a stacked wafer body consisting of a plurality of sets (4) of two semiconductor wafers and a heat sink plate (3) interposed there between, with an end of the heat skin plate being exposed at at least one of the side surfaces of the stacked Wafer body as discussed by the authors.Abstract:
A multi-layer semiconductor device comprising: a stacked wafer body (7) consisting of a plurality of sets (4) of two semiconductor wafers (1) and a heat sink plate (3) interposed therebetween, an end of the heat sink plate (3) of each set (4) of wafers being exposed at at least one of the side surfaces of the stacked wafer body (7), there being an intermediate connecting circuit (8) provided for connecting circuits in each set of wafers (4), the intermediate connecting circuit (9) being provided on at least one side surface other than the surface at which the ends of the heat skin plates (3) are exposedread more
Citations
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Patent
Three-dimensional read-only memory
TL;DR: A read-only memory structure, having a three dimensional arrangement of memory elements, is described in this paper, where memory elements are partitioned into multiple memory levels and each memory level is stacked on top of another.
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TL;DR: In this paper, a semiconductor wafer array comprising a plurality of wafers (10-18) of semiconductor material is provided with cone-shaped or pyramid-shaped vias (25).
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TL;DR: In this paper, a method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry in specific areas on their respective face surfaces.
Patent
Integrated multichip memory module structure
Claude L. Bertin,Wayne J. Howell,Erik L. Hedberg,Howard Leo Kalter,Goodon Aasaa Kerii Jiyunia +4 more
TL;DR: In this article, a memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices, and a preformed electrical interface layer is employed at one end of the memory sub unit to electrically interconnect the controlling logic chip with the memory chips comprising the sub unit, thereby producing a dense multichip integrated circuit package.
Patent
Controlled impedence interposer substrate
Solomon I. Beilin,William T. Chou,David Kudzuma,Michael G. Lee,Michael G. Peters,James J. Roman,Som S. Swamy,Wen-chou Vincent Wang,Larry L. Moresco,Teruo Murase +9 more
TL;DR: In this article, an interposer substrate for mounting an integrated circuit chip to a substrate, and method of making the same, is shown, which comprises power supply paths and controlled impedance signal paths that are substantially isolated from each other.
References
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Patent
Stacked semiconductor device with sloping sides
TL;DR: In this article, a stacked semiconductor device is defined, where a plurality of semiconductor layers integrated with semiconductor elements are stacked with an insulating layer interposed between two adjacent layers.
Patent
Circuit module with enhanced heat transfer and distribution
TL;DR: In this article, a circuit module (10) having enhanced heat transfer and distribution characteristics which is particularly adapted for use in high speed electronic digital computers is presented, which includes a circuit board assembly (12) with a plurality of electronic devices (26) such as integrated circuits, mounted on the circuit board (28).
Patent
Interconnected multiple circuit module
TL;DR: In this article, the specification discloses an interconnected multiple circuit module (10) including a connector assembly (14) for interconnecting two circuit modules (12) each having at least one circuit board assembly (16), the connector assembly includes pins (26) extending through the circuit board assemblies and a free connector block (28) for receiving the pins in opposite ends.
Patent
Detector array module-structure and fabrication.
John C. Carson,Stewart A. Clark +1 more
TL;DR: In this paper, a photo-detector array module (PDA) consisting of a stack of semiconductor chips having integrated circuitry on each chip is presented. But the module is not suitable for the use of cameras.
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3d-coaxial memory construction and method of making
TL;DR: In this article, a semiconductor memory in which integrated circuit chips each containing semiconductor flip-flop memory elements are mounted to respective ones of a plurality of batch-fabricated, pressure-stacked electrically conductive wafers so as to form a compact, essentially all metal, three-dimensional memory structure.