Patent
Multiprocessor including system for pipeline processing of multi-functional instructions
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TLDR
A data processor as mentioned in this paper is an instruction decoding unit which includes an encoding circuit encoding bit positions of "1" or "0" of a register list field represented by a bit string consisting of binary digits representing the register number from which or to which data to be transferred is transferred.Abstract:
A data processor, comprises: an instruction decoding unit which includes an encoding circuit encoding bit positions of "1" or "0" of a register list field represented by a bit string consisting of "1" and "0", in binary digits representing the register number from which or to which data to be transferred is transferred, and decodes the instruction to output a control code including the decoded result of an operation code field and the register number; an instruction executing unit which accesses a memory and executes the instruction; and instruction execution control unit which controls the instruction executing unit in accordance with the control code outputted from the instruction decoding unit to load data to the register indicated by the register number from a memory area, or to store data into the memory area from the register indicated by the register number, and is capable of executing the instruction for transferring plural data between the memory and register at high efficiency, by encoding the register list by an priority encoder to obtain the register number in an instruction decoding stage.read more
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References
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Patent
Data processing unit with pipelined operands
TL;DR: In this article, a data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed.
Patent
Address translation and generation system for an information processing system
TL;DR: In this article, an address converting and generating system for an information processing system is described, which includes a segment type memory and an instruction having an operation code part, a field for specifying a register for loading a physical address representing a segment relative address, and a displacement for specifying logical address.
Patent
Register bank change including register to register transfer in a data processing system
TL;DR: In this article, a data processing system has a function to perform data processing by specifying one of a plurality of register groups according to an instruction, which contains information for indicating a change from one register group to another register group and information for specifying a desired one or two or more registers in said register group.
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Data processor providing plural decoders for effecting fast register selection
TL;DR: In this paper, a data processor has an execution unit, an instruction register in which macro instructions having a register field are set for specifying registers in the execution unit and a micro ROM in which micro instructions containing a register instruction field were set.
Patent
External memory accessing system
TL;DR: In this paper, a new and improved external memory accessing system for use in a microprocessor is presented, which includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions.