Patent
Multiprocessor system with each processor executing the same instruction sequence and hierarchical memory providing on demand page swapping
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TLDR
In this paper, a hierarchical virtual memory management scheme is proposed to keep the most-used data in the local memory, page swapping with disk memory is through the global memory; the globalmemory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory.Abstract:
A computer system employs multiple CPUs, all executing the same instruction stream, with multiple, identical memory modules storing duplicates of the same data and accessable by all the CPUs, providing global memory. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously. Each CPU has its own fast cache and also a local memory not accessable by the other CPUs. A hierarchical virtual memory management arrangement for this system employs demand paging to keep the most-used data in the local memory, page-swapping with the global memory. Page swapping with disk memory is through the global memory; the global memory is used as a disk buffer and also to hold pages likely to be needed for loading to local memory. The operating system kernal is kept in local memory. This arrangement is particularly useful in fault-tolerant computer systems.read more
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References
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Patent
Massively parallel processor computer
TL;DR: The massively parallel processor architecture as discussed by the authors enables very high speed processing of large amounts of ordered, parallel data, including spatial translation by shifting or "sliding" of bits vertically or horizontally to neighboring processing elements.
Patent
Multiprocessor multisystem communications network
Allen James Conard,Wendy Bohle Bartlett,Hoke Stephens Johnson,Steven Derek Fisher,Richard Oliver Larson,John Charles Peck +5 more
TL;DR: In this paper, a plurality of multiprocessor systems is arranged in a high speed network to allow any processor in one system to communicate with another processor in another system, and buffer locations are managed so that they can request an adjacent node to stop transmitting packets if the buffer is becoming full from that direction and request resumption of transmission of packets as the buffer empties.
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TL;DR: The architecture of a special-purpose multiprocessor, hierarchically structured and functionally distributed, having ditributed cache memory for local processing and a common applictions task manager in each microcomputer is described in this article.
Patent
Operations controller for a fault tolerant multiple node processing system
TL;DR: In this paper, a fault tolerator for an operations controller of a multiple-node fault tolerant processing system has been proposed, which includes an error file for storing the content of all received inner node error reports, an error handler for generating a base penalty count for each node based on the contents of the errors recorded in the error file and for excluding each node from the operation of the multiple node processing system whose base penalty counts exceeds an exclusion threshold.
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