Patent
Output buffer with switchable output impedance
Gopal Raghavan,Dhruv Jain +1 more
Reads0
Chats0
TLDR
An output buffer with a switchable output impedance designed for driving a terminated signal line is presented in this article. But the buffer is not designed to be used for a memory system, as it is not suitable for such a system.Abstract:
An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.read more
Citations
More filters
Patent
Methods and apparatus of stacking DRAMs
TL;DR: In this paper, large capacity memory systems are constructed using stacked memory integrated circuits or chips, which are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
Patent
Configurable memory circuit system and method
Suresh Natarajan Rajan,Keith R. Schakel,Michael John Sebastien Smith,David T. Wang,Frederick Daniel Weber +4 more
TL;DR: In this paper, a memory circuit system and method are provided in the context of various embodiments, where an interface circuit remains in communication with a plurality of memory circuits and a system.
Patent
Memory circuit system and method
Suresh Natarajan Rajan,Michael John Sebastian Smith,Keith R. Schakel,David T. Wang,Frederick Daniel Weber +4 more
TL;DR: In this paper, a memory circuit system and method for communication with a plurality of DRAM integrated circuits and a system is presented, where the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.
Patent
Memory module with memory stack and interface with enhanced capabilities
Suresh Natarajan Rajan,Keith R. Schakel,Michael John Sebastian Smith,David T. Wang,Frederick Daniel Weber +4 more
TL;DR: In this paper, a memory module, which includes at least one memory stack, comprises a plurality of DRAM integrated circuits and an interface circuit, and the interface circuit interfaces the memory stack to a host system so as to operate memory stack as a single DIMM integrated circuit.
Patent
Memory systems and memory modules
TL;DR: In this article, the authors present a memory module that includes at least one memory chip, and an intelligent chip coupled to the memory module, where the intelligent chip is configured to implement at least a part of a RAS feature.
References
More filters
Patent
Bi-directional output buffer
Chung-Hsiao R. Wu,Jong Jyh-Ming +1 more
TL;DR: In this paper, a bi-directional output buffer includes active termination and separate driving and receiving impedances, and the buffer is configured such that resistive components are shared in both the driving and the receiving modes.
Patent
Adjustable impedance driver network
TL;DR: In this article, a variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output, each transmission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.
Patent
Output buffer with time varying source impedance for driving capacitively-terminated transmission lines
TL;DR: In this paper, the output buffer for driving a capacitivelyterminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1 to a voltageV2, a second portion while the buffer remains fixed at V2; a third portion while it transitions from V2 to V3, and a fourth portion during the buffer's remaining fixed position at V3.
Patent
Memory bus termination
TL;DR: In this paper, the memory bus line is terminated with one or more transistors of an output buffer that are used to drive the memorybus line during a memory write, and a machine-readable medium is described.
Patent
Dynamic impedance controlled driver for improved slew rate and glitch termination
TL;DR: In this article, a buffer driver, driving signals with edge transitions onto a transmission line is controlled to improve slew rate and glitch termination by controlling the driver to have a low impedance during a period when edge transitions are taking place.