Patent
Peripheral controller for coupling data buses having different protocol and transfer rates
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TLDR
In this article, a peripheral controller is provided for controlling data transfers between peripheral devices operably on one type of data bus to devices operable on a second data bus, where an intermediate buffer is utilized so that data is read into one memory block from the sending data bus and read out of another memory block to the receiving data bus.Abstract:
A peripheral controller is provided for controlling data transfers between peripheral devices operably on one type of data bus to devices operable on a second data bus. An intermediate buffer is utilized so that data is read into one memory block from the sending data bus and read out of another memory block to the receiving data bus. Controls are provided to prevent overwriting data which has not been transmitted and to prevent data transfers from the buffer until at least one block of memory has been filed.read more
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Systems and methods for managing resource utilization in information management environments
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TL;DR: In this article, the authors present methods and systems for providing differentiated service that may be employed, for example, to deliver content or services in a network environment, including both differentiated information service and differentiated business service.
References
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Patent
Clock pulse control system for microcomputer systems
TL;DR: A clock pulse control system for microcomputer systems includes a central processing unit, a plurality of first input/output units, and a second unit having the same frequency or a different frequency to operate the second unit as mentioned in this paper.
Patent
Apparatus and method for providing synchronization between processes and events occurring at different times in a data processing system
Jacques Michel Jean Bienvenu,Claude Carre,Patrick Dufond,Duc L. Tuong,Philippe-Hubert deRivet,Henri Verdier,John J. Bradley,Benjamin S. Franklin +7 more
TL;DR: The semaphore data structure as mentioned in this paper is a data structure which stores representations of processes awaiting particular events or alternatively storing representations of events awaiting processes, and is used to connect a process and a non-simultaneously occurring event or resource.
Patent
Communication multiplexer having a variable priority scheme using a read only memory
TL;DR: In this article, a data processing system includes a number of input/output devices coupled to a communication multiplexer which polls the devices in a predetermined order, and the communication controller rearranges the polling order to provide highest priority to an input or output device in a receive mode that is currently operative and to give lowest priority to a transmit device that has just completed its operation.