Patent
Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration
TLDR
In this paper, a pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration is presented, which comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit module and a back level analog to digital conversion module which are sequentially connected in series.Abstract:
The invention discloses a pipelined analog-digital converter (ADC) capable of carrying out background digital calibration. The pipelined (ADC) comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit modules and a back level analog-to-digital conversion module which are sequentially connected in series, wherein each calibrated level circuit module is connected with a corresponding digital calibrated level circuit; the quantized value output port of the level circuit module and the quantized value output port of a back level analog-to-digital conversion module are respectively connected with a time delay and dislocation summation module; and the output end of the time delay and dislocation summation module is sequentially and reversely connected in series in the digital calibrated level circuit. The pipelined analog-to-digital converter provided by the invention has the advantages that the thinking is inventive, the analog circuit has a simple structure, a pseudo random number generator and a multi-way selection switch are additionally arranged on the foundation of the existing technical structure, and the working of other analog circuits can not be unaffected in the working process; and simultaneously, the principle of the digital circuit segment is simple and is easy to realize, the error of the pipelined ADC can be reduced obviously, the linearity of the pipelined ADC can be improved, and the dynamic properties of the pipelined ADC can be improved.read more
Citations
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Patent
Comparator applied to low-power-consumption Pipeline ADCs (analog-to-digital converter)
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TL;DR: In this article, a time-interleaved assembly line ADC system and a sequential operation method of the system were presented. But the authors did not specify the sampling speed of the ADC system.
Patent
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TL;DR: In this article, a digital background correction method applicable to a pipelined analog-to-digital converter was proposed, where by adding pseudorandom quantity, the information of sampling capacitance mismatch and harmonic coefficients of an operation amplifier can be obtained to further correct the main output of the P2D converter.
References
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Patent
Correlation-based background calibration of pipelined converters with reduced power penalty
TL;DR: In this paper, a correlation-based background calibration of pipelined analog-to-digital converters with a reduced power penalty is proposed. But the method is not suitable for the use of a large amplitude signal.
Patent
Pipeline structured A/D converter with high speed and high precision
TL;DR: In this article, an error measure circuit and a circuit of correcting digital error in the A/D convertor are presented, which is composed of logic circuit and oscillators with their oscillating period direct proportional to magnitude of capacitance.
Patent
Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof
Wenhai Ni,Rui Wang +1 more
TL;DR: In this article, a pipeline analog-to-digital converter and a quick calibration method of capacitance mismatch thereof is described, which is characterized by carrying out inverted order calibration from a level circuit module of the last level.