Patent
Pseudo random signal producing circuit
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TLDR
In this paper, a pseudo-random signal producing circuit includes a generator 110 for generating a first pseudo random signal having a bit width a (a being an integer not smaller than 1).Abstract:
A pseudo random signal producing circuit includes a generator 110 for generating a first pseudo random signal having a bit width a (a being an integer not smaller than 1), a generator 120 for generating a second pseudo random signal having a bit width b (b being an integer not smaller than 1 and different from a), a matrix calculator 130 for carrying out matrix calculation upon the first and the second pseudo random signals to produce a calculation result signal having a bit width (a*b), an N-bit shift register 200 responsive to the calculation result signal having the bit width (a*b) for producing an output pseudo random signal having a bit width N (N being a divisor of (a*b)), and a frequency-division clock generator 300 for driving a pseudo random data generator 100.read more
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References
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Patent
Pseudo-random generator
TL;DR: In this article, a secure block cypher encoder was proposed to generate cryptographically strong pseudo-random bit streams, where each bit is related to an inner product between each input to the encoder and a second seed (h).
Patent
Bent sequence code generator
TL;DR: In this article, a method and apparatus for generating a bent sequence code as a transform of an m-sequence code is presented, which can be used to generate bent m-sequences.
Patent
Pseudorandom number generator
TL;DR: The pseudorandom number generator as mentioned in this paper consists of a M-sequence generator whose output is fed in parallel to a hardware shuffling device, which generates the random numbers with the desired statistical properties.
Patent
Method of and an apparatus for generating pseudo-random numbers
TL;DR: In this paper, a T-ary counter (101) was proposed to generate pseudo-random numbers at high speed with sufficient cryptographical security with sufficient security, and the apparatus consisted of a modulus memory (103) for outputting a prime number read out from T prime numbers prepared therein according to a value of the count number; an n-bit register (102) for registering and outputting an nbit value in synchronization with the clock signal; an expanded affine transformation circuit (104) was presented to output the intermediate number as one of the pseudo random numbers in
Patent
Block pseudo-noise generating circuit
Katherine G. Brown,Zhengou Gu +1 more
TL;DR: In this article, the LFSR (40, 50) is used to calculate a PN sequence using Fibonacci form, such that when an offset is calculated from a known state, the bits of the new state comprise a block of sequence bits.