Patent
Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip
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TLDR
A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic and microcode bugs.Abstract:
A VLSI chip debug and production test apparatus that allows an engineer to view the state of hundreds of signals internal to a chip in real-time without probing, which greatly simplifies the isolation of circuit, speed, logic, and microcode bugs. For production testing, it also provides the ability to check the state of these internal signals on a clock-by-clock basis. The mechanism uses a gated XOR-input serial shift-register cell (10), which is stepped out underneath major buses in otherwise unpopulated areas of the chip. Several of these cell groups are linked together to form a scanout path of the desired length, the operation of which is controlled with a single input pin (40). Output data is channeled through a shared output pin (19) to a VLSI tester (16). In the tester (16) the data (19) is checked and accumulated by back-end software over multiple test-loop iterations, and formatted into a readable form.read more
Citations
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Proceedings ArticleDOI
FRITS - a microprocessor functional BIST method
TL;DR: A novel functional Built-in-Self-Test (BIST) method for microprocessors is described, based on the fundamental principle that complex chips have embedded functionality that can be used to implement a comprehensive self-test strategy.
Patent
Self-testing multi-processor die with internal compare points
TL;DR: A self-test circuit on the microprocessor die accumulates errors for each CPU and reports these errors to an inexpensive external tester as mentioned in this paper, and the results from each CPU core written back to the shared cache are also compared, and arbitration allows one CPU to write the result to the share cache while results from other CPU's are discarded.
Book
System-on-Chip Test Architectures: Nanometer Design for Testability
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
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Computer-aided design system to automate scan synthesis at register-transfer level
Laung-Terng Wang,Xiaoqing Wen +1 more
TL;DR: In this paper, a method and system to automate scan synthesis at register-transfer level (RTL) is presented. But this method is not suitable for the verification of scan HDL code.
References
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Patent
Method and apparatus for assisting in debugging of a digital computer program
TL;DR: In this paper, a technique for assisting in the detection of errors and malfunctions in the operation of a digital computer program is described, which includes circuitry for connection to the back plane of a computer for receiving representations of the program instructions executed by the computer.
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