scispace - formally typeset
Patent

Scanning method and apparatus for current signals having large dynamic range

TLDR
In this article, a method for scanning information off a processing plane where the information is contained in a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude.
Abstract
There is disclosed herein apparatus and a method for scanning information off a processing plane where the information is contained in a current signal having a very small amplitude and which can change signs and vary in amplitude by as much as five orders of magnitude. The preferred embodiment of the apparatus uses a pair of CMOS pass transistors connected to the individual processing elements and the row select lines. The pass transistors, when turned on, couple the output current from the processor containing the desired information to a column line. The column line is connected to a current to voltage converter in the form of a differential input amplifier having a non linear feedback circuit comprised of two diode connected CMOS transistors operating in the subthreshold region. The non linear feedback circuit provides an exponential transfer function which compresses the dynamic range of the output current from the processor to a smaller and more useable output range for an output voltage. The negative feedback to the inverting input coupled to the column line stabilizes the voltage on the column line to virtual ground thereby eliminating the delay associated with driving the parasitic capacitance of the column line with the very small output current from the processor in an attempt to substantially change the voltage of the column line.

read more

Citations
More filters
Patent

Capacitance to code converter with sigma-delta modulator

TL;DR: An apparatus and method for converting a capacitance measured on a sensor element to a digital code is described in this article, where the switching capacitor is in a feedback loop of the sigma-delta modulator.
Patent

Apparatus and method for reducing average scan rate to detect a conductive object on a sensing device

TL;DR: In this paper, a switch circuit is configured to couple each of a plurality of plurality of capacitive sense elements and a pluralityof capacitance sensors in different modes, such that the switch circuit can couple the plurality of sense elements to individual ones of the two or more of the sense elements in one of the groups.
Patent

Touch-sensor with shared capacitive sensors

TL;DR: In this article, a method and apparatus to implement a touch-sensor device using shared capacitive sensors is described, where the sensor elements of the first, second, and third plurality of sensor elements are interspersed and disposed in a repetitive sequence along a movement path of a conductive object.
Patent

Touch detection techniques for capacitive touch sense systems

TL;DR: In this article, a technique for recognizing and rejecting false activation events related to a capacitance sense interface includes measuring a measured capacitance value of an element to determine a baseline capacitance values for the capacitance sensor.
Patent

Matrix array image sensor chip

TL;DR: In this article, a matrix array image sensor integrated circuit chip including horizontal and vertical scanning means with the sensor cells within columns of the array being associated with an analogue charge sense amplifier.
References
More filters
Patent

Image pickup apparatus

TL;DR: In this article, a current mirror circuit, formed of an input transistor and an output transistor with first current-carrying electrodes joined together to a voltage reference point and with control electrodes connected together, amplifies the signal current.
Patent

Single gate line interlace solid-state color imager

TL;DR: In this paper, a solid-state color imager with a light sensing element and a switching element composed of two parallel-connected FET devices is presented, with one of the gates being activated for a first field and the other for scanning for a second field.
Patent

Logarithmic converter circuit arrangements

TL;DR: A logarithmic converter circuit comprises a LTLF generating device and a transconductance amplifier connected in parallel with the LTL generating device, with the transconductances in the range of about two micromhos to about twenty millimhos as mentioned in this paper.
Patent

Signal conditioning circuit

TL;DR: A signal conditioning circuit includes a logarithmic signal compression circuit for compressing wide dynamic range input signals to a dynamic range which is a predetermined portion of the dynamic range of an output utilization apparatus as discussed by the authors.
Patent

Electronic addressing system to read mosaic matrices of optical-electronic elements

TL;DR: In this article, an electronic addressing system to read matrices of optical-electronic elements, wherein the elements are of any type, for example photoresistors, photodiodes, light emitters, and the like, is presented.