Patent
Self-aligned gate field effect transistor with schottky barrier drain and source
R Wakefield,J Cunningham,M Hswe +2 more
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TLDR
In this paper, a self-altering gate technology is used in the construction of a field effect transistor in a large-scale environment, where MANY SUCH ALIGNMENTS MUST be made SIMULTANTEOUSLY.Abstract:
A LOW PARASITIC CAPACITANCE FIELD EFFECT TRANSISTOR IS FABRICATED BY THE UTILIZATION OF A SELF-ALIGNING GATE TECHNIQUE. A METAL GATE IS FORMED AND THEN, EMPLOYING THE GATE AS A MASK, LOW TEMPERATURE SCHOTTKY BARRIER SOURCE AND DRAIN JUNCTIONS ARE FORMED. THE TECHNIQUE IS PARTICULARLY USEFUL IN THE FABRICATION OF THE FIELD EFFECT TRNASISTOR AS AN ELEMENT OF A LARGE INTEGRATED CIRCUIT WHERE MANY SUCH ALIGNMENTS MUST BE MADE SIMULTANTEOUSLY. D R A W I N Gread more
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Patent
Insulated gate field effect transistor having passivated schottky barriers to the channel
Daniel E. Grupp,Daniel Connelly +1 more
TL;DR: In this paper, the Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm 2.
Patent
Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
Daniel E. Grupp,Daniel Connelly +1 more
TL;DR: In this article, an electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor is described. But the interface layer does not have an interface mechanism.
Patent
Complementary field-effect transistor integrated circuit device
TL;DR: In this paper, the authors proposed an integrated circuit with Schottky barrier source and drains (SB-IGFET) to eliminate the parasitic pnpn structure which causes the latchup problem in conventional CMOS structures.
Patent
Method of forming plasma etched semiconductor contacts
TL;DR: In this paper, it was shown that if the silicon semiconductor is converted to a metal silicide in the region where contact is to be made subsequently, its plasma etch rate can be reduced sufficiently to avoid overetching.
Patent
Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
TL;DR: In this article, a self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs are formed by depositing a source/drone in a recess such that it remains only in the recess.