Patent
Semi-floating gate device and manufacturing method therefor
TLDR
In this paper, a semi-floating-gate device with a gated p-n junction diode is described, which uses the floating gate to store information and realizes charging or discharging of the floating-gate through a Gated P-N junction Diode.Abstract:
The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.read more
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AMOLED (Active Matrix/Organic Light-Emitting Diode) pixel driving circuit and method
TL;DR: In this article, an organic light-emitting diode (OLED) pixel driving circuit with an embedded tunneling field effect transistor is presented. And the driving transistor can be used to change the threshold voltage of the driving transistors and further change a driving current.
Patent
Active matrix organic light emitting diode pixel drive circuit and driving method thereof
TL;DR: In this paper, an active matrix organic light emitting diode pixel drive circuit and a driving method for pixel drive circuits is presented. But the authors do not specify the driving method of pixel drive transistors.
Patent
Semi-floating gate storage device, manufacturing method thereof and semi-floating gate storage device array
TL;DR: In this paper, the authors proposed a semi-floating gate storage device array, which comprises at least one U-shaped groove formed in a semiconductor substrate, a buried source region formed in the semiconductor substrategies at the bottom part of the U-shape groove, two drain regions formed at two sides of the u-shaped hole and two floating gates for storing charges.
Patent
Semi-floating gate device and manufacturing method
TL;DR: In this paper, a semi-floating gate device consisting of a semiconductor substrate of a first doping type, a convex body formed in on the surface of the semiconductor surface, a drain region of the second doping type formed on one side of the substrate, and a source region of a second doping Type formed on the other side of a substrate, a first layer insulation thin film, a floating gate of the first doping Type, and the control gate, wherein the drain region is connected with the convex Body, the channel region and the body are covered with the
Patent
Memory unit structure
Kang Yong,Chen Bangming +1 more
TL;DR: In this paper, a memory unit structure which comprises an SOI (silicon on insulator) wafer and a gate structure with a semi-floating gate is described.
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Patent
Nonvolatile semiconductor memory device and method of manufacturing the same
TL;DR: In this article, a nonvolatile semiconductor memory device is defined, which includes a channel portion, a drain and a source, first and second floating gates, and a control gate.
Patent
NOR flash memory cell with high storage density
TL;DR: In this article, a NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate, and a transmission line coupled to the second source/drain region.
Patent
Vertical NAND flash memory array
TL;DR: In this article, the use of vertical floating gate memory cells in NAND architecture memory strings, arrays, and devices is described, which allow for an improved high density memory devices or arrays that can take advantage of the feature sizes semiconductor fabrication processes are generally capable.
Patent
Semiconductor photosensitization device, production method and application thereof
TL;DR: In this article, a semiconductor photo-sensitization device consisting of a source electrode, drain electrode, a control grid, a floating grate region, a substrate, and a p-n node diode for connecting a floating gate region and a drain electrode is presented.
Patent
Vertical channel dual-grate tunneling transistor and preparation method thereof
TL;DR: In this article, a semiconductor device consisting of an N type tunneling transistor and a P type MOS (Metal Oxide Semiconductor) was described. But the authors did not reveal the power consumption of the chip.