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Patent

Tab-type semiconductor process

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TLDR
In this article, the TAB (Tape Automated Bonding) process uses single-layer tapes to form a semiconductor structure, and the bottom surface of the chip preferably remains uncovered so that it can be electrically connected to ground or another potential.
Abstract
A TAB (Tape Automated Bonding) process uses single-layer tapes to form a semiconductor structure. Beam leads on a metal tape are "inner-lead bonded" to a chip. Each chip site on a specially-formed plastic tape has a central portion and a peripheral portion which are bonded to the chip so that the central portion forms a protective cover over the chip and the peripheral portion acts as a support for the beam leads during probe testing, excising and forming operations, etc. The bottom surface of the chip preferably remains uncovered so that it can, if appropriate, be electrically connected to ground or another potential.

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Patent

Semiconductor connection components and methods with releasable lead support

TL;DR: In this paper, a connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps, and leads extend across these gaps so that the leads are supported on both sides of the gap.
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Connection components with frangible leads and bus

TL;DR: In this article, an electrically conductive leads are adapted to be bonded to contacts on a semiconductor chip by breaking the frangible sections of the leads so as to disconnect the second ends of the leading from the bus and engage the leads with the contacts of the semiconductor.
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Compliant integrated circuit package and method of fabricating the same

TL;DR: In this article, a thermally conductive protective structure has been used for semiconductor chip packages, which includes an indentation open to a front side and a flange surface at least partially surrounding the indentation and facing to the front of the structure.
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TL;DR: In this paper, a method of making a pad array chip carrier package is disclosed, where a semiconductor device is bonded to a ceramic substrate by wirebonding, tab bonding or flip chip bonding, and the entire assembly is then placed into a mold cavity and registered against the temporary support substrate.
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Method of making chip mountings and assemblies

TL;DR: In this article, a dielectric layer is first provided having a central region, slots and a peripheral region, and a metallic structure is also provided having bonding pads on the central region and leads electrically connected to the bonding pads and to a plating bus disposed in the peripheral region.
References
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Manufacture of semiconductor device

TL;DR: In this article, the cross patterns for conformity with eyes for the full automatic bonder are shaped at the nose sections of the leads at one diagonal positions of a lead frame, and a semiconductor element is placed on the island of the lead frame to which the patterns are formed.
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Gang bonding interconnect tape process and structure for semiconductor device automatic assembly

TL;DR: In this article, a continuous tape is employed in the automatic assembly of semiconductor devices, each one comprising a plurality of metal fingers, each pattern includes fingers having an inward extension that terminates in a configuration that mates with the contact pattern of the semiconductor device.
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TL;DR: In this article, the bonding layer for connecting wires to semiconductor chips with contact fingers, or contact strips, on a substrate carrier is formed as spongy, microporous structure, applied to discrete positions of the contact strips by screen printing, and secured to the metallic connecting strip by a diffusion zone.
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TL;DR: In this paper, the authors proposed to improve the yield by placing many IC chips on a substrate, measuring together the ICs, performing a burn-in test, further dividing ICs into pieces, and placing only good ones on a hybrid integrated circuit substrate.