Patent
Testable LSI device incorporating latch/shift registers and method of testing the same
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TLDR
In this article, a testable LSI chip incorporating memory blocks, such as RAM and ROM, and random logic circuitry, and a testing method thereof are disclosed, where a front-stage peripheral logic circuit block and rear-stage PLC are provided on their output side and input side, respectively, with the flip-flops in correspondence to the input and output nodes of the memory block.Abstract:
A testable LSI chip incorporating memory blocks, such as RAM and ROM, and random logic circuitry, and a testing method thereof are disclosed. A front-stage peripheral logic circuit block and rear-stage peripheral logic circuit block connected to the input and output modes of a memory block are provided on their output side and input side, respectively, with the flip-flops in correspondence to the input and output nodes of the memory block. The flip-flops on the output side and flip-flops on the input side are each connected to form a shift register. In testing the front peripheral logic block, the test result is latched in the flip-flops on the output side and then the contents are shifted out for reading. In testing the rear-stage peripheral logic circuit block, a bit pattern for testing is shifted-in and latched in the flip-flops on the input side and then supplied to the rear-stage peripheral logic circuit block under test. The front and rear-stage peripheral logic circuit blocks are tested independently of the memory block.read more
Citations
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References
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Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
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