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Proceedings ArticleDOI

Topological synthesis procedure for circuit integration

W. Engl, +1 more
- pp 138-139
TLDR
A computer-aided topological layout of components and wiring in integrated circuits will be presented based on a new kind of graph which accounts for all technological restrictions, as well as possibilities.
Abstract: 
A computer-aided topological layout of components and wiring in integrated circuits will presented based on a new kind of graph which accounts for all technological restrictions, as well as possibilities.

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Citations
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Journal ArticleDOI

Mathematical models for the circuit layout problem

W. vanCleemput
- 01 Dec 1976 - 
TL;DR: An improved model is suggested that is based on the concept of partially oriented graph and contains more topological information than earlier models, which reduces the need for special constraints on the graph embedding algorithm.
Journal ArticleDOI

A proper model for testing the planarity of electrical circuits

A. J. Goldstein, +1 more
- 01 Jan 1973 - 
TL;DR: The question of whether an electrical circuit can be laid out on a plane, without resorting to crossovers or multilayer wiring, is usually answered by testing the planarity of a graph representing the circuit.
Journal ArticleDOI

Computer-aided topological design for integrated circuits

W. Engl, +2 more
- 01 Nov 1973 - 
TL;DR: Component placement and wire routing are looked at as a coupled surface layering problem on two planes and transformed into a graph theoretic synthesis problem by neglecting the lateral dimensions of components and wiring.
Proceedings ArticleDOI

An integrated circuit layout design program based on a graph-theoretical approach

N. Sugiyama, +4 more
TL;DR: A graph-theoretical method, with wiring and placement problems considered simultaneously, has resulted in the development of a computer program affording automatic layout design of single-layer IC chips on smallest possible areas.
Proceedings ArticleDOI

On the topological aspects of the circuit layout problem

W. M. vanCleemput
TL;DR: This paper investigates the topological and geometrical characteristics of the circuit layout problem and presents a topological layout procedure that can be especially useful for integrated circuit layout.