Patent
Variable latency method and apparatus for floating-point coprocessor
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TLDR
In this paper, a programmable latency (a programmable number of clock cycles) needed for an operation completion is determined from a formula including the system clock cycle time which the unit will be specified to operate under.Abstract:
A programmable latency (a programmable number of clock cycles) needed for an operation completion. The required latency for a pipe is determined from a formula including the system clock cycle time which the unit will be specified to operate under. The latency is preprogrammed by setting the count of a timer accordingly to provide at least the minimum number of clock cycles necessary to cover the time required to do the computation. Separate timers are independently set for arithmetic logic unit (ALU) operations, multiply operations, logical operations and divide and square root operations.read more
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Patent
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Patent
Floating point circuit with configurable number of multiplier cycles and variable divide cycle ratio
TL;DR: In this paper, an intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers.
Patent
Floating-point unit constructed of identical modules
TL;DR: In this paper, a configuration logic is proposed to enable the exponent processing unit of only the first module, and disables those of the remaining modules, and further inhibits modules whose mantissa processing units are not required for processing a mantissa of a given precision from affecting the results produced by the remaining mantissa processor units.