Showing papers on "Automatic test pattern generation published in 1981"

Automatic Test Generation for Stuck-Open Faults in CMOS VLSI

Abstract: Because of its relative low power dissipation, intermediate speed, and high density, CMOS (Complementary Metal Oxide Semiconductor) will emerge as one of the leading VLSI technologies. Therefore, testing CMOS VLSI circuits is very important. The conventional stuck-at fault assumptions are not sufficient for modeling some faults that are peculiar to CMOS circuitry, specifically the stuck-open faults. These faults are sequential in nature. This means that when a fault occurs in a combinational circuits, the circuit behaves as a sequential circuit. Therefore, special test pattern generation techniques are necessary to test this type of faults. In this paper, we present an algorithm which uses the conventional stuck-at list to detect some stuck-open faults. Some modifications of the conventional testing procedure are necessary. Such modifications and their associated programming effort are expected to be straight forward. For the stuck-open faults that cannot be detected by the conventional stuck-at test list, a second algorithm is described that generates the tests for such faults. The algorithm generates the test if such a test exists. If not, the fault is declared as undetectable. First, we will discuss the stuck-open fault and its peculiarity to CMOS circuitry. Second, we will describe the step-by-step algorithms used to generate a complete test list for this type of fault. Finally, a small example circuit will be used to illustrate the new test generation technique and some conclusive remarks will be given.

Using attributed grammars to test designs and implementations

Abstract: We present a method for generating test cases that can be used throughout the entire life cycle of a program. This method uses attributed translation grammars to generate both inputs and outputs, which can then be used either as is, in order to test the specifications, or in conjunction with automatic test drivers to test an implementation against the specifications.The grammar can generate test cases either randomly or systematically. The attributes are used to guide the generation process, thereby avoiding the generation of many superfluous test cases. The grammar itself not only drives the generation of test cases but also serves as a concise documentation of the test plan.In the paper, we describe the test case generator, show how it works in typical examples, compare it with related techniques, and discuss how it can be used in conjunction with various testing heuristics.

Multiple Fault Testing of Large Circuits by Single Fault Test Sets

Abstract: A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault detection test sets in combinational circuits. The theory is unique in that it provides greatest lower bounds on the coverage capability of all possible circuits of concern by a simple table-look-up process. All the results known so far in this area are seen to be special cases of the theory. The more important contribution of the theory, however, is seen in its predictions made for reconvergent internal fan-out circuits. Most unexpectedly, the multiple fault coverage of such circuits by single fault test sets is discovered to be extremely precarious. Such results clearly have alarming implications in LSI and VLSI testing.

LSI logic testing — An overview

Abstract: The development of large scale integration (LSI) testing is reviewed. The paper concentrates on the testing of logic components and presents in-depth discussions of the methods of fault modeling, test pattern generation, fault simulation, and design for testability. It is shown how these methods are used in the design of components and how they can be used in support of design automation. Finally, a brief account of test equipment and test data preparation is given.

Design for autonomous test

Abstract: A technique for modifying networks so that they are capable of self test is presented. The major innovation is partitioning the network into subnetworks with sufficiently few inputs that exhaustive testing of the subnetworks is possible. Procedures for reconfiguring the existing registers into modified linear feedback shift registers (LFSR's) which apply the exhaustive (not pseudorandom) test patterns or convert the responses into signatures are described. No fault models or test pattern generation programs are required. A method to modify CMOS circuits so that exhaustive testing can be used even when stuck-open faults must be detected is described. A detailed example using the 74181 ALU is presented.

Random testing of integrated circuits

Abstract: The paper concerns fault detection by applying a random input sequence simultaneously to a circuit under test and to a reference circuit. The objective is to determine the length of the input sequence to be applied, to obtain a given detection quality (detection probability). The paper gives a summary of the results which have been obtained for combined circuits, memories, SSI, and MSI sequential circuits.

Multiple fault testing of large circuits by single fault test sets

Abstract: A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault detection test sets in combinational circuits. The theory is unique in that it provides greatest lower bounds on the coverage capability of all possible circuits of concern by a simple table-look-up process. All the results known so far in this area are seen to be special cases of the theory. The more important contribution of the theory, however, is seen in its predictions made for reconvergent internal fan-out circuits. Most unexpectedly, the multiple fault coverage of such circuits by single fault test sets is discovered to be extremely precarious. Such results clearly have alarming implications in LSI and VLSI testing.

A 16-bit self-testing multiplier

Abstract: A self-testing circuit is presented, i.e., a circuit able to signal out any inner fault. It is a 16-bit serial-parallel multiplier, based on a 2-bit Booth algorithm; data are coded in two's complement. The use of a rather cheap self-testing technique based on parity predicting results in the realization of a `self-testing-only' circuit requiring only about 25 percent extra silicon area. This realization permitted to study the feasibility of self-testing circuits. Critical points are also pointed out, such as the testing of I/O pins.

New Measures of Testability and Test Complexity for Linear Analog Failure Analysis

Abstract: The failure analysis of analog electronic systems is characterized by numerous, difficult problems. Assessing the testability and test complexity of a given system is one such problem. In fact, robust, quantitative measures of these important features have not been available to the analog testing community. This paper introduces new measures for both testability and test complexity which: 1) are quantitative, 2) are capable of handling multiple faults, and 3) have a well-defined interpretation. These measures are based upon published results from optimal experiment designs as developed in the discipline of systems identification. Parameter testability is defined in terms of information (in the sense of Fisher) return, while test complexity is functionally related to the experiment time required to achieve specified accuracy with regard to the uncertain parameters of interest. Thus both of the new measures introduced depend, not only upon the specific system at hand, but also upon the experimental conditions used in performing the tests. The results of this approach lead to quantitative measures that have optimality features based upon the Cramer–Rao bound.

Random Fault Analysis

Abstract: A method is presented for performing rapid Test Pattern Evaluation (TPE) using classical statistical analysis This method is applicable regardless of the types of faults being considered, the likelihood of the fault occuring, or the technique used for fault simulation A subset of the complete fault list is selected using random sampling techniques, and the fault coverage (percentage of faults detectable by the given test pattern) is estimated and confidence limits about this estimate are given This technique is useful for LSI as well as VLSI Test Pattern Evaluation in that only a small subset of the total fault list need be analyzed to determine the fault coverage within a few percent

Optimization of access points for automatic test program generation and fault location in large analogue circuits and systems

Abstract: The paper develops a methodology for the automatic test program generation (ATPG) for a large analogue circuit subject to component drifts. An optimization algorithm developed selects the best set of intermediate access points for a.c. and d.c. tests of the circuit.During ATPG, faults are simulated by varying each component over a wide range. Voltages measured at all available nodes are thus used in the pre-processing stage of node selection. An optimization procedure based on the discriminating power of measurements and separability between fault signatures is used to select the best set of frequencies applicable for all nodes in a.c. testing. A preamplifier and control amplifier of 56 components is chosen as Unit Under Test (UUT) to demonstrate the ATPG. The fault isolation scheme used is based on the nearest neighbour rule.The rexlationship between diagnosability and number of test features is shown to follow the customary Pareto type curve. However, four carefully chosen nodes and three carefully chosen test frequencies are shown to give an adequate level of diagnosability. The whole scheme is implemented automatically using a minicomputer interfaced to the UUT.