Showing papers on "BCH code published in 1986"

Signal processing apparatus for correcting decoding errors

Abstract: There is a signal processing apparatus for use in the error correction field for correcting errors in systems such as Reed Solomon code. This apparatus has three kinds of cells which execute the proceses in the decoding of the BCH code: namely, a syndrome cell to produce syndromes; a GCD (greatest common divisor) cell to produce an error position polynomial and an error evaluation polynomial; and an evaluation cell to estimate and correct errors in position and size. The required cells are one-dimensionally arranged in accordance with the error correcting capability of the code which is used. The algorithm for the signal processes in the conventional communication line is modified to the algorithm suitable for parallel processing. The signal processes can be executed using parallel processors due to the pipeline processes. Those dedicated cells can be realized by the hardwares, respectively. Each cell is controlled by only reference clock and synchronizing signal and the input and output data are time-sequentially multiplexed in the cell or process. Thus, this apparatus is fitted for multi-error correction and can be formed as an LSI because the circuit scale is small.

On-the-fly decoder for multiple byte errors

Abstract: Multiple-error-correcting Reed-Solomon or BCH codes in GF(2 b ) can be used for correction of multiple burst errors in binary data. However, the relatively long time required for decoding multiple errors has been among the main objections to applying these schemes to high-performance computer products. In this paper, a decoding procedure is developed for on-the-fly correction of multiple symbol (byte) errors in Reed-Solomon or BCH codes. A new decoder architecture expands the concept of Chien search of error locations into computation of error values as well, and creates a synchronous procedure for complete on-the-fly error correction of multiple byte errors. Forney's expression for error values is further simplified, which results in substantial economies in hardware and decoding time. All division operations are eliminated from the computation of the error-locator equation, and only one division operation is required in the computation of error values. The special cases of fewer errors are processed automatically, using the corresponding smaller set of syndromes through a single set of hardware. The resultant decoder implementation is well suited for LSI chip design with pipelined data flow. The implementation is illustrated with an example.

Radio pager having local- and wide-area reception modes

Abstract: In a radio paging system, radio paging signals contain a BCH (31, 16) format address and a BCH (31, 21) format address which are sent from a central station. The paper is assigned first and second BCH format user identification codes corresponding respectively to the BCH (31, 16) and BCH (31, 21) addresses. The pager has mode select switches for selecting the BCH (31, 16) address for local area reception or BCH (31, 21) address for wide area reception. When a paging signal is received, a coincidence is detected between the selected address and the corresponding BCH user identification code. When the coincidence is detected, the user is alerted to the reception by a paging signal. An appropriate channel is established in the local or wide service area.

Apparatus for and methods of decoding a BCH code

Abstract: Apparatus for decoding a Bose-Chaudhuri-Hocqueng­ hem (BCH) code can correct double errors, using a modifica­ tion of the Chien search method. The decoding apparatus comprises circuits (2, 3) for forming syndromes S1 and S3, a circuit (5) for forming S1², a circuit (6) for forming S1³, a circuit (7) for forming (S1³ + S3), and a Chien search circuit (8) in which the error-location polynomial σ′(x) = S1x² + S1² x + S1³ + S3 is solved, thereby enabling correction of errors of two or less. With this apparatus, there is no need to perform a dividing process, and a high decoding processing speed can be realised without using either a PLA or a ROM.

Method and apparatus for decoding BCH code

Abstract: Apparatus for decoding BCH code can correct double errors using a modification of the Chien search method. This decoding apparatus comprises circuits to form syndromes S1 and S3; a circuit to form S1 2 ; a circuit to form S1 3 ; a circuit to form (S1 3 +S3); and Chien search circuit, in which the error-location polynomial σ(x)=(S1x 2 +S1 2 x+S1 3 +S3) is solved, thereby correcting errors of two or less. With this apparatus, there is no need to perform a dividing process, and a high decoding processing speed can be realized without using any PLA or ROM.

Algorithms and architectures for error correcting codes (decoding, reed-solomon)

Abstract: Ever since Shannon demonstrated the unexpected possibility of virtually error-free communication over noisy channels, work in coding theory has been aimed towards finding practical encoding and decoding schemes. Berlekamp's fast algorithm for decoding Reed-Solomon and BCH codes was a major step in this direction; however, the intrinsic structure of this algorithm hinders its use on the high rate channels of the future. Additionally, Berlekamp's algorithm is not entirely regular, complicating its VLSI implementation (e.g. testability, modularity, design time). By re-examining the underlying structure of the problem, new algorithms and architectures are developed that overcome these limitations. A particular implementation has more than twice the throughput of Berlekamp's algorithm, and is ideally suited for VLSI implementation. The philosophy adopted here is novel in that the algorithms are designed to match the VLSI hardware constraints instead of vice versa. A matrix approach to the derivation leads to an algorithm that can be implemented on a parallel architecture with local communication between processing elements. A polynomial approach yields an algorithm that can be implemented on a serial-input, concurrent architecture with local communication. The invocation of scattering theory for this derivation both provides physical intuition and readily displays the impact of algorithmic choices on the implementation architecture. The matrix and polynomial approaches are unified to obtain the Micro-level Euclidean (MLE) Algorithm, which defines a family of VLSI-compatible implementations for decoding Reed-Solomon and BCH codes. Two particular concurrent processing architectures for implementing the MLE algorithm are detailed to determine area and time performance. It is shown that these architectures require less than half the area of other alternatives to Berlekamp's algorithm. In the process of deriving the MLE algorithm, several related results are discovered. One outcome is a better understanding of Berlekamp's algorithm, including the meaning of inner products and also a derivation from a particular form of the Euclidean algorithm. This allows us to explicitly exhibit the tradeoffs between Berlekamp's algorithm and the implementations of Euclidean algorithm presented here. Other results in partial realization theory and connections to Hankel and Toeplitz matrix inversion are also obtained.

Relations among parameters of codes (covering radius, automorphism groups, bounds, t-dense)

Abstract: Let R denote the covering radius of an n,k,d code. We show that (DIAGRAM, TABLE OR GRAPHIC OMITTED...PLEASE SEE DAI) This improves the Griesmer bound to n (GREATERTHEQ) max g(k,d),g(k,d) + R - (d - (IR-PERP)d/2('k)(IL-PERP)) , where (DIAGRAM, TABLE OR GRAPHIC OMITTED...PLEASE SEE DAI) If the code is cyclic with the generator polynomial g(x), then the bound R (LESSTHEQ) n - k + 1 - (IR-PERP)wt(g(x))/2(IL-PERP) is obtained. Furthermore if g(x) is irreducible, then upper bounds on R are found using Waring's problem. New classes of 1-error-correcting quasi-perfect codes are also derived. We also give necessary and sufficient conditions on C to attain one of the so-called "Norse bounds". We give improved upper bounds on the covering radii of shor- tened codes. Exact covering radii of shortened codes are determined for some t-dense codes including, among others, s-error-correcting BCH codes (s = 1,3), RM codes (of ords 1 and m - 3), and some Q.R. codes. Most of these codes are shown to be normal. Results on the number of cosets of maximum weight of shortened codes are derived. Even subcodes are shown to be shortened codes, proving the normality of many extended codes. We also show that many codes meeting the Griesmer bound with eqality are normal. In addition, we give simplifications and improvements of some known results on normality. We determine the t-transitivity and t-homogeneity of the auto- morphism groups of binary linear cyclic codes. An improvement of the Roos bound is also given. We also give an improved result on the cardinality of nonlinear codes. Finally, we exploit the action of a permutation group on a binary linear code to give a faster-than-conventional algorithm to compute its covering radius. In the case of a cyclic code an improvement in time complexity by a factor of the order of the automorphism group is achieved.

Bch coding decoding system

Abstract: PURPOSE: To increase processing capacity by using plural number of arithmetic circuits consisting of selector circuits, multipliers, adders and registers. CONSTITUTION: A processing element (PE) consists of the selector circuit 1 of multiple-input multiple-output or multiple-input single-output, multipliers 2 and 3 on a Galois field having an output from the selector circuit 1 as an input, an adder 4 on the Galois field adding the outputs from the multipliers 2 and 3, and register circuits 5∼7 accumulating the output from the adder 4 and the output from the selector circuit 1. With using plural number of the PEs, a BCH code is encoded. COPYRIGHT: (C)1988,JPO&Japio

Device control system by error correction code

Abstract: PURPOSE:To improve the control capability of a PCM decoder by using a special code possible for error detection of (N+2) bit when an error correction code BCH(I,J) has an error correction capability of (N+1) bits. CONSTITUTION:In case of a BCH(7,3) code, for example, a quotient of a transmission code T(x) divided by a generation polynomial G(x) of the correction code BCH(7,3) is 4 bits and 16 codes exist. In case of 0-2-bit error, the code of quotient of T(x)divided by G(x) is 15 codes and the remaining codes 1011 have an error with 3-bit or over without gail. Then if the code 1011 is generated, it is discriminated as an error of >=3 bits, the control such as suppression of noise in voice and switching of active/spare system is attained.

Fast Reed-Solomon Decoder

Abstract: High-speed decoder intended for use with Reed-Solomon (RS) codes of long code length and high error-correcting capability. Design based on algorithm that includes high-radix Fermat transform procedure, which is most efficient for high speeds. RS code in question has code-word length of 256 symbols, of which 224 are information symbols and 32 are redundant.

Decoder for single error 2,3,4-bit error detection bch code

Abstract: PURPOSE:To attain error correction and detection of a BCH code by calculating a coefficient sigmai of an error location polynomial through the combination of different syndromes and discriminating whether the error is corrected or only detected based on a criterion expression established under the condition that the sigmais are all equal. CONSTITUTION:The criterion expression Z of the single error 2, 3, 4 bit error detection BCH code is expressed in equation 1. With S0=S1=S3=0, it is processed as no error. When the Z1 is true, it is discriminated as 1 bit error and when the Z1 is false, it is discriminated that 2-4-bit (or more) error takes place. The 2-4-bit error can be detected 100%. Further, the adequacy of the criterion expression is proved easily.

Laboratory evaluation of a mobile radio data system

Abstract: A mobile communications system has been built to study the parameters affecting data transmitted at 9.6 Kb/s over a laboratory simulated VHF mobile radio channel with additive white gaussian noise and Rayleigh fading. The signal is demodulated by a conventional mobile FM radio and its error distribution is recorded. The performances of different modulation schemes are presented and their BER are compared in a static and a fading environment. The simple and pratical technique of optimum threshold diversity switching by pre-detection of the signal's envelope is used at the receiver to combat fading. The data sequences received are recorded and analysed by computer in order to determine the error distributions and the performances of BCH and Reed-Solomon error-correcting codes.

High speed decoder for double error correction 3-bit error detection bch code

Abstract: PURPOSE:To constitute easily a decoder for double error correction 3-bit error detection DEC-TED BCH code by adding an error discrimination circuit to a known decoder for double error correction DEC BCH code. CONSTITUTION:An output of an OR circuit 5 goes to logical 1 when a single or a double error exists, because an output of a ZD4 goes to logical 1 with S 1+S3=0 and then with Z=S0(S 1+S3)=0, an output of an AND circuit 10 goes to logical 0 and an error correction signal is fed to an AND circuit 9. In case of a triple error, Z is logical 1 and an output of the OR circuit 5 is logical 0, then an output of the AND circuit 10 goes to logical 1 to detect the error. In order to correct the error, all elements are substituted in an equation 1 and whether or not each of them is a root is checked in parallel. S1alpha is obtained from S1alpha 6 and S 1alpha is obtained from S 1alpha7 and a CI8 detects whether or not the sum of both is S 1+S3, and an output of the CI8 and an error correction signal are inputted to the AND circuit 9. A location where its output signal is logical 1 indicates the error location.