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Showing papers on "Bitonic sorter published in 1982"


Journal ArticleDOI
Yasuura1, Takagi1, Yajima1
TL;DR: A new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting is designed, suitable for VLSI implementation.
Abstract: We propose a new parallel sorting scheme, called the parallel enumeration sorting scheme, which is suitable for VLSI implementation. This scheme can be introduced to conventional computer systems without changing their architecture. In this scheme, sorting is divided into two stages, the ordering process and the rearranging one. The latter can be efficiently performed by central processing units or intelligent memory devices. For implementations of the ordering process by VLSI technology, we design a new hardware algorithm of parallel enumeration sorting circuits whose processing time is linearly proportional to the number of data for sorting. Data are serially transmitted between the sorting circuit and memory devices and the total communication between them is minimized. The basic structure used in the algorithm is called a bus connected cellular array structure with pipeline and parallel processing. The circuit consists of a linear array of one type of simple cell and two buses connecting all cells for efficient global communications in the circuit. The sorting circuit is simple, regular and small enough for realization by today's VLSI technology. We discuss several applications of the sorting circuit and evaluate its performance.

69 citations


Journal ArticleDOI
TL;DR: This paper contains a description of a data sorting machine intended for VLSI construction with simultaneous compare/sort operations so that the amount of time needed for sorting N words is proportional to N.

9 citations


Proceedings ArticleDOI
01 Jan 1982
TL;DR: A two stage parallel sorting scheme is presented in which in the first stage the input file is divided into a number of subfiles and sorted in parallel using the conventional heap sort algorithm.
Abstract: A two stage parallel sorting scheme is presented in which in the first stage the input file is divided into a number of subfiles and sorted in parallel using the conventional heap sort algorithm. The second stage then merges the sorted sub-files in parallel. It is shown that a given input file of size n can be sorted in 0(n) time using 0(log n) processors. The speed-up ratio, which is a measure of the effectiveness of parallel processing, with respect to the best sequential algorithm, is asymptotically proportional to log n, which is optimal in the number of processors used.

3 citations


Journal ArticleDOI
TL;DR: The algorithm here proposed sorts k wagons, using m sidings, in O(logjfc) cycles and is, unlike the polyphase merge briefly discussed by Colin et al., well suited to trains.
Abstract: This paper proposes an alternative solution to the problem posed by Colin et al. The algorithm here proposed sorts k wagons, using m sidings, in O(logjfc) cycles and is, unlike the polyphase merge briefly discussed by Colin et al., well suited to trains. It is equally applicable to other distributive sorting problems and was originally devised by the author for sorting punched cards in an electromechanical card sorter. It may be of more general interest because non-radix distributive sorts are rare in the literature (for example, Knuth does not discuss them).

2 citations