Showing papers on "Carry flag published in 1967"

Binary multiplier employing multiple input threshold gate adders

Abstract: 1,195,410. Binary multiplier. R.C.A. CORPORATION. 29 Dec., 1967 [17 Jan., 1967], No. 59103/67. Heading G4A. A binary multiplier for multiplying a multiplicand word YnYn-1 ... Y 0 by a multiplier word x n x n-1 ... x 0 , comprises in combination means for producing an output signal indicative of x 0 y 0 ; a plurality of multiple bit adder means, each consisting of interconnected threshold gates each for producing signals indicative of the sum and carry of a group of bits chosen from A, xy, S and W bits, where A is a partial product and consists of the logical product of an x bit and a y bit, xy is a logical product, S is a sum bit, and W is a carry bit; means for concurrently applying to each adder means a group of signals chosen from signals representing A, x, y, S and W bits, where the signals representing S and W bits applied to any adder means are derived from another adder means; and means for interconnecting said adder means in such a way as to produce sum signal outputs indicative of the sums of partial products of the multiplicand and multiplier bits which sum signal outputs represent the bits other than x 0 y 0 of the product of the multiplicand and multiplier words. A three by three bit multiplier is shown in Fig. 11 multiplying x 3 x 2 x 1 by y 3 y 2 y 1 . The least significant product bit S 1 is produced by a majority gate 156. S 2 is produced by a 2-input adder comprising three threshold gates 158, 160, 162, gate 158 being a simple majority gate having equally weighted inputs. The three gates produce a sum bit S 2 and a carry bit W 3 , the latter being fed to the next most significant stage. Similar three input or two input adders where indicated are used to produce the product and the carries. A more complicated adder is shown in Fig. 13 where partial products A 0 , D 0 , G 0 , H 0 , K 0 , No shown ringed are applied to gates as separate x and y bits. All other partial products are formed in threshold AND gates prior to bring supplied to the three or more input adders. The inputs to each threshold gate are the terms included in the brackets and the carry bits produced and supplied to the next more significant column are arranged and indicated in square boxes. Sum bits produced either as the final product or by threshold gates where more than one such gate is used to add the partial products in a column are shown in broken circles. The subscript in the final sum term indicates the significance of the stage while the superscript indicates the number of stage delays.