Showing papers on "Carry flag published in 1981"

Arithmetic unit for use in data processing systems

Abstract: A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.

Arithmetic unit for use in a data processing system for computing exponent results and detecting overflow and underflow conditions thereof

Abstract: A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.

Charge coupled device ripple adder with nearly instantaneous carry propagation

Abstract: A ripple adder is implemented as a charge coupled device in such a manner that each carry bit propagates between succeeding full adder stages substantially simultaneously as each stage computes the sum of its two bits, so that the addition in each full adder stage may be carried out in parallel rather than in succession. The ith one of the CCD full adder stages includes charge transfer means for receiving two bits of charge, namely the ith bits of the two n-bit words which are to be summed. First and second charge storage means are provided, each having the capacity to store one bit of charge only, so that excess charge will cause an overflow. Means for sensing overflow charge stored in the second charge storage means is connected to a carry bit charge injector in the ith +1 adder stage.

Time read system

Abstract: PURPOSE:To decrease the number of scanning points of a scanner required for a read of time information by composing carry information, showing that a hardware timepiece is in time information carry operation, of one bit. CONSTITUTION:It is shown that hardware timepiece TIM is in carry operation of time information. Only one carry bit C is provided to row ROW-0. Therefore, each binary number covering month tens digit MOT and second unit SU is contained in two lines ROW-0 and ROW-1 in a scanning matrix including carry bit C.